4.20.1. Register values

Table 4.71 lists the register values for the SSMC for typical operation the PISMO memory expansion with static memory devices and a 25MHz system clock.

Note

The platform.a library contains memory setup routines. See Building an application with the platform library.

The SSMCCR register at 0x200 is always loaded with 0x1 to select clock ratio of 1:1 with the clock always running.

Table 4.71. Register values for PISMO CS0 (SMC CS4)

AddressName of SSMC registerValueDescription
0x10080080SMBIDCYR0x0FIdle Cycle Control Register for bank
0x10080084SMBWSTRDR0x1FRead Wait State Control Reg bank
0x10080088SMBWSTWRR0x1FWrite Wait State Control Reg Bank
0x1008008CSMBWSTOENR0x01Output Enable Assertion Delay
0x10080090SMBWSTWENR0x00Write Enable Assertion Delay
0x10080094SMBCR0x00303021Control Register for memory bank. The default bus with is set by CFGWIDTH.
0x10080098SMBSR-Status Register for bank (read-only)
0x1008009CSMBWSTBRDR0x0FBurst Read Wait state Control Reg

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