4.21.1. PrimeCell modifications

The PrimeXsys System Controller used in the baseboard FPGA implements only the SYS_CTRL and peripheral ID registers. These registers support the following functionality:

The function of the bits in the SYS_CTRL register at address 0x10001000 is listed in Table 4.73.

Note

TIMCLK is 1MHz. REFCLK is 32.768kHz.

Table 4.73. SYS_CTRL register

BitsFunction
[31:24]

Reserved. Use read-modify-write to preserve value.

[23]

Watchdog enable override. If 0, the enable output is derived from the REFCLK source. If 1, the enable output is forced HIGH.

[22]

Timer 3 enable override. If 0, the enable output is derived from the Timing Reference Select signal. If 1, the enable output is forced HIGH.

[21]

Timer 3 enable/ Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK.

[20]

Timer 2 enable override. If 0, the enable output is derived from the Timing Reference Select signal. If 1, the enable output is forced HIGH.

[19]

Timer 2 enable/ Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK.

[18]

Timer 1 enable override. If 0, the enable output is derived from the Timing Reference Select signal. If 1, the enable output is forced HIGH.

[17]

Timer 1 enable/ Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK.

[16]

Timer 0 enable override. If 0, the enable output is derived from the Timing Reference Select signal. If 1, the enable output is forced HIGH.

[15]

Timer 0 enable/ Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK.

[14:10]

Reserved. Use read-modify-write to preserve value.

[9]Remap status. This read-only bit returns the remap status.
[8]Remap clear request. Set this bit to disable memory remapping and return to normal mapping with dynamic memory selected for memory accesses to the region 0x00000000-0x00FFFFFF.
[7:0]

Reserved. Use read-modify-write to preserve value.


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