| |||
Home > Glossary |
This glossary lists abbreviations used in the User Guide.
Analog to Digital Converter. A device that converts an analog signal into digital data.
Advanced Audio CODEC Interface.
Advanced High-performance Bus. The ARM open standard for on-chip buses.
Advanced Microcontroller Bus Architecture.
Advanced Peripheral Bus. The ARM open standard for peripheral buses. This design is optimized for low power and minimal interface complexity.
ARM eXtended Debugger.
Advanced eXtensible Interface. The ARM open standard for high-performance and high-frequency buses.
Bill Of Materials. A list of all the parts used on the printed circuit board and any specific build instructions for board variants.
Color Liquid-Crystal Display.
COder DECoder for converting between analog and digital audio signals.
Digital to Analog Converter. A device that converts digital data into analog level signals.
Debug Communications Channel.
Double Data Rate, DRAM with high-speed data access.
Disk-On-Chip. A non-volatile flash memory device with an interface that simplifies file accesses. Also called NAND flash referring to the logic gates used internally. The memory can only be accessed sequentially in blocks.
Dynamic Memory Controller.
Direct Memory Access.
Dynamic Random Access Memory.
Data Set Ready, a UART flow-control signal.
Data Terminal Ready, a UART flow-control signal.
Embedded Trace Buffer.
Embedded Trace Macrocell.
Field Effect Transistor.
Field Programmable Gate Array.
Generic Interrupt Controller.
General Purpose Input/Output.
Generic Test Chip. A packaging and signal assignment specification for test chips.
In Circuit Emulator. A interface device for configuring and debugging processor cores.
Integrator Compact Platform.
Interface Module used to connect tile-format boards to an Integrator system.
Interface Module used to connect tile-format boards to an Integrator system. This module has an FPGA that provides the interface between the Integrator signals and the tile signals.
Input/Output.
Intellectual Property.
Joint Test Action Group. The committee which defined the IEEE test access port and boundary-scan standard.
Keyboard/Mouse Interface.
Liq uid Crystal Display.
Light Emitting Diode.
Media Access Control. A layer in the Ethernet specification.
MultiMedia Card Interface.
MultiMedia Card.
Multi-ICE is a system for debugging embedded processor cores using a JTAG interface. See ICE.
Non-volatile memory. NAND refers to the type of logic gate used internally. See DOC.
Non-volatile memory. NOR refers to the type of logic gate used internally. Any memory address can be accessed randomly.
On-The-Go, a USB specification.
Printed Circuit Board.
Peripheral Component Interconnect. A computer bus for attaching peripherals.
PHYsical layer. The layer in the Ethernet specification that describes the physical interface.
Platform Independent Storage Module. Memory specification for plug in memory modules.
Programmable Logic Device.
Phase-Locked Loop, a type of programmable oscillator.
Power On Reset.
Random Access Memory.
RealView ICE. A system for debugging embedded processor cores using a JTAG interface. See also ICE.
Real-Time Clock.
RealView Debugger.
Static Random Access Memory.
Smart Card Interface.
Secure Digital memory card specification.
Static Memory Controller.
Soft Macrocell Model of a CPU core.
Synchronous Serial Port.
Tightly Coupled Memory. Memory present inside the test chip that typically runs at or near the processor speed.
Trace Port Analyzer.
Universal Asynchronous Receiver/Transmitter.
Universal Serial Bus.
Video Graphics Array.