This glossary lists abbreviations used in the User Guide.

ADC

Analog to Digital Converter. A device that converts an analog signal into digital data.

AACI

Advanced Audio CODEC Interface.

AHB

Advanced High-performance Bus. The ARM open standard for on-chip buses.

AMBA

Advanced Microcontroller Bus Architecture.

APB

Advanced Peripheral Bus. The ARM open standard for peripheral buses. This design is optimized for low power and minimal interface complexity.

AXD

ARM eXtended Debugger.

AXI

Advanced eXtensible Interface. The ARM open standard for high-performance and high-frequency buses.

BOM

Bill Of Materials. A list of all the parts used on the printed circuit board and any specific build instructions for board variants.

CLCD

Color Liquid-Crystal Display.

CODEC

COder DECoder for converting between analog and digital audio signals.

DAC

Digital to Analog Converter. A device that converts digital data into analog level signals.

DCC

Debug Communications Channel.

DDR

Double Data Rate, DRAM with high-speed data access.

DOC

Disk-On-Chip. A non-volatile flash memory device with an interface that simplifies file accesses. Also called NAND flash referring to the logic gates used internally. The memory can only be accessed sequentially in blocks.

DMC

Dynamic Memory Controller.

DMA

Direct Memory Access.

DRAM

Dynamic Random Access Memory.

DSR

Data Set Ready, a UART flow-control signal.

DTR

Data Terminal Ready, a UART flow-control signal.

ETB

Embedded Trace Buffer.

ETM

Embedded Trace Macrocell.

FET

Field Effect Transistor.

FPGA

Field Programmable Gate Array.

GIC

Generic Interrupt Controller.

GPIO

General Purpose Input/Output.

GTC

Generic Test Chip. A packaging and signal assignment specification for test chips.

ICE

In Circuit Emulator. A interface device for configuring and debugging processor cores.

Integrator/CP

Integrator Compact Platform.

Integrator/IM-LT1

Interface Module used to connect tile-format boards to an Integrator system.

Integrator/IM-LT3

Interface Module used to connect tile-format boards to an Integrator system. This module has an FPGA that provides the interface between the Integrator signals and the tile signals.

I/O

Input/Output.

IP

Intellectual Property.

JTAG

Joint Test Action Group. The committee which defined the IEEE test access port and boundary-scan standard.

KMI

Keyboard/Mouse Interface.

LCD

Liq uid Crystal Display.

LED

Light Emitting Diode.

MAC

Media Access Control. A layer in the Ethernet specification.

MCI

MultiMedia Card Interface.

MMC

MultiMedia Card.

Multi-ICE

Multi-ICE is a system for debugging embedded processor cores using a JTAG interface. See ICE.

NAND flash

Non-volatile memory. NAND refers to the type of logic gate used internally. See DOC.

NOR flash

Non-volatile memory. NOR refers to the type of logic gate used internally. Any memory address can be accessed randomly.

OTG

On-The-Go, a USB specification.

PCB

Printed Circuit Board.

PCI

Peripheral Component Interconnect. A computer bus for attaching peripherals.

PHY

PHYsical layer. The layer in the Ethernet specification that describes the physical interface.

PISMO

Platform Independent Storage Module. Memory specification for plug in memory modules.

PLD

Programmable Logic Device.

PLL

Phase-Locked Loop, a type of programmable oscillator.

POR

Power On Reset.

RAM

Random Access Memory.

RVI

RealView ICE. A system for debugging embedded processor cores using a JTAG interface. See also ICE.

RTC

Real-Time Clock.

RVD

RealView Debugger.

SRAM

Static Random Access Memory.

SCI

Smart Card Interface.

SD

Secure Digital memory card specification.

SMC

Static Memory Controller.

SMM

Soft Macrocell Model of a CPU core.

SSP

Synchronous Serial Port.

TCM

Tightly Coupled Memory. Memory present inside the test chip that typically runs at or near the processor speed.

TPA

Trace Port Analyzer.

UART

Universal Asynchronous Receiver/Transmitter.

USB

Universal Serial Bus.

VGA

Video Graphics Array.