3.2. Tile interconnections

The tile site on the baseboard enables the board to be used with Logic Tiles. The tiles are stackable and each tile has three connectors on the top and bottom (HDRX, HDRY, and HDRZ). See RealView Logic Tile header connectors for details.

Note

ARM support the use of Logic Tiles at the PB-A8 tile site. Support is available through Applications Notes provided on the Versatile Family CD and on the ARM Infocenter at: infocenter.arm.com

The bus usage on the tiles depend on the type of baseboard and the combination of tiles used. For PB-A8, HDRX (Bus T1X) carries the mux AXI master bus signals and HDRY carries the mux AXI slave bus signals (Bus T1Y). HDRZ (Bus T1Z) carries the additional I/O signals required by the Logic Tile (clocks, resets, JTAG etc). See Figure 3.5 for a simplified diagram of the main tile and system bus routing.

Figure 3.5. Tile site and main system bus routing

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Note

On the PB-A8 CLCD, UART2, and UART3 interfaces can be sourced from the baseboard or logic implemented in the FPGA on an attached Logic Tile. The CLCD source and the UART 2 and UART3 source are controlled independently by signals DVI_SEL and UART_SEL respectively.

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