3.12.2. PLL

The test chip contains an on-board PLL with a VCO and digital circuitry. The test chip clocks are provided by the Output divider. The clock source for the Output divider can be either the output of the PLL or the reference clock to the test chip, REFCLK. A glitchless mux is included to ensure clean switching between the Output divider clock sources. A simplified diagram of the PLL and Output divider is shown in Figure 3.12.

Figure 3.12. Test chip PLL and output divider

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The PLL can generate two discrete clocks, CLK and AXICLK. Each clock is an integer multiple of the input reference clock, REFCLK. The output depends on the PLL operating mode. The modes are bypass mode or at-speed mode. Figure 3.13 shows the clock frequency equations that describe the behavior of CLK and AXICLK as simple functions of BYPASS.

Figure 3.13. PLL clock frequency equations

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Note

In the above equations PLLODIV = 0 is not supported. Therefore, if PLLODIV = 0, assume PLLODIV = 1.

The divider values are set by writing to the PLL initialization register SYS_PLL_INIT. Default divider values are loaded during power-on initialization and do not need to be changed for normal operation. If you need to adjust the CLK and AXICLK frequencies, see PLL initialization register, SYS_PLL_INIT for details.

VCO specification

The VCO is a voltage-controlled oscillator integrated into the PLL. Table 3.3 shows the specification for the VCO. Unless stated otherwise, all data in the table refers to worst case conditions.

Table 3.3. VCO specification

VCO characteristic Data
Reference frequency range 5MHz - 200MHz
VCO output frequency range 200MHz - 2GHz
Reference divider values 1-16, bit range [3:0]
Feedback divider values 1-4096, bit range [11:0]
Output divider values 1-256, bit range [7:0]
Output duty cycle, all corners with tolerance 50% ± 2%
Cycle-to-cycle jitter, peak-to-peak, maximum 2% output cycle
Lock time, maximum allowed at reset 300 reference cycles
Relock time, when divider ratios are changed < 50 VCO output cycles
Frequency overshoot, maximumfull frequency40%
half frequency50%
Low frequency supply noise, estimated maximum, peak-to-peak 10% AVDD
Low frequency sub-threshold noise, estimated maximum, peak-to-peak 10% AVDD

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