3.5.3. Memory controllers

The Northbridge implements memory controllers for:

Static memory controller, SMC

The Northbridge implements the PrimeCell PL354 Static Memory Controller, an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM.

The PrimeCell PL354 is part of the PL350 series of area-optimized SRAM and NAND memory controllers with on-chip bus interfaces that conform to the AMBA Advanced eXtensible Interface (AXI) protocol.

On the PB-A8 the PrimeCell PL354 supports:

  • Pseudo Static Random Access Memory (PSRAM)

  • NOR flash devices with an SRAM interface

  • Ethernet and USB controllers with an SRAM interface

  • SRAM expansion memory via a PISMO interface.

See Static Memory Controller, SMC for details of PB-A8 usage and the ARM PrimeCell Static Memory Controller (PL350 series) Technical Reference Manual (ARM DDI 0380) for full programming details.

Dynamic memory controller, DMC

The Northbridge implements the PrimeCell PL340 Dynamic Memory Controller, an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM.

The PL340 DMC is a high-performance, area-optimized SDRAM memory controller with on-chip bus interfaces that conform to the AMBA Advanced eXtensible Interface (AXI) protocol.

On the PB-A8 the PrimeCell PL340 supports:

  • Synchronous Dynamic Random Access Memory (DDR SDRAM)

  • a shared external memory bus interface.

Note

To reduce the pinout requirements, the Northbridge uses the PL340 DMC in conjunction with the PrimeCell PL220 External Bus Interface (EBI) to implement a shared external memory bus interface. See ARM PrimeCell External Bus Interface (PL220) Technical Reference Manual (DDI 0249) for details.

See Dynamic Memory Controller, DMC for details of PB-A8 usage and the ARM PrimeCell Dynamic Memory Controller (PL340) Technical Reference Manual (ARM DDI 0331) for full programming details.

Single master direct memory access controller, SMDMAC

The Northbridge implements the PrimeCell PL081 Single Master DMA Controller, an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral that is developed, tested, and licensed by ARM.

The PrimeCell PL081 is an AMBA AHB module, and connects to the Advanced High-performance Bus (AHB). Two DMA channels, each supporting a unidirectional transfer are provided. There are 16 peripheral DMA request lines and each peripheral connected to the PL081 can assert either a single DMA request, or a burst DMA request, the DMA burst size is programmable.

In the Northbridge the PrimeCell PL081 supports:

  • eight channels of direct memory access (with DMAC flow control only)

  • DMA access to the tile site

  • two selectable DMA channel to peripheral mappings

See Single Master Direct Memory Access Controller, SMDMAC for details of PB-A8 usage and the ARM PrimeCell Single Master DMA Controller (PL081) Technical Reference Manual (ARM DDI 0218) for full programming details.

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