3.14. Interrupts

The PB-A8 implements four custom Generic Interrupt Controllers (GICs) in the Southbridge.

Note

The GICs have 16 software interrupts, INT[15:0] and 16 reserved software interrupts, INT[31:16]. The external interrupts are allocated from INT[32] upwards. Some of these external interrupts are reserved. See Table 4.44 for details.

Figure 3.18 shows the PB-A8 interrupt routing to the GICs.

Figure 3.18. Internal and tile site interrupt routing

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The GICs accept interrupts from peripherals in the Northbridge, Southbridge, on-board peripherals, and the tile site. The GICs generate nFIQ and nIRQ signals to the Cortex-A8 test chip and the tile site:

GIC0

generates the Cortex-A8 nIRQ

GIC1

generates the Cortex-A8 nFIQ

GIC2

generates the tile site nIRQ

GIC3

generates the tile site nFIQ.

The COMMRX and COMMTX debug signals from the Cortex-A8 are available as interrupt sources. COMMRX and COMMTX are used for the Debug Communication Channel (DCC) on ARM processors. The DCC enables you to communicate with your application over the JTAG interface without stopping the processor. DCC can be polled or interrupt driven, but using interrupts is faster.

See Generic Interrupt Controller, GIC for details of the GIC programmer’s interface, the full PB-A8 interrupt allocation, and guidelines on interrupt handling.

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