3.5.5. Multiplexed AXI interfaces

The Northbridge interfaces to the tile site via two multiplexed 64-bit AXI buses. Bus multiplexing is required at the tile site to reduce the pin count. Header HDRX carries a master multiplexed AXI bus from the tile site to the baseboard, and header HDRY carries a slave multiplexed AXI bus from the tile site to the baseboard.

See Application Note AN151, available on the Versatile Family CD or the ARM Infocenter, for details of the multiplexing scheme and RealView Logic Tile header connectors for details of the baseboard signal pinout.

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