4.3.17. PCI status register, SYS_PCI_STAT

The PCI status register, SYS_PCI_STAT at 0x1000006C monitors the status of the PCI-X bridge (PCI6520) component.


ARM do not recommend changing the register default values as this may affect the reliability of the PCI interface.

Figure 4.17 shows the register bit assignment.

Figure 4.17. SYS_PCI_STAT register

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The function of the register bits are listed in Table 4.19.

Table 4.19. SYS_PCI_STAT register bit assignments

[31:12]Write ignored, read as zero0x00000Undefined
[11:10]Write ignored, read as zerob00Undefined
[9]Read/WriteP_M66ENb166MHz PCI-X enable
[8]Read/WriteP_100MHZb1Clock control
[7]Read/WritePCIMODEb0PCI mode: b0 = PCI-X host to PCI-X bridging b1 = PCI-X host to PCI bridging
[6:5]Read/WritePCIFREQb01PCI frequency: b00 = 33MHz b01 = 66MHz b10 = 100MHz b11 = 133MHz
[4]Read/WritePCIBUS64b164-bit PCI bus enable
[3:0]Read/WritePPLL_PA0x7PLL range: 0x1 = PPLL_RANGE300_600MHz 0x3 = PPLL_RANGE150_300MHz 0x4 = PPLL_RANGE100_200MHz 0x5 = PPLL_RANGE75_150MHz 0x7 = PPLL_RANGE50_100MHz

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