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4.11. Generic Interrupt Controller, GIC

A custom Generic Interrupt Controller (GIC) is implemented in the Southbridge.

Table 4.43. Generic Interrupt Controller implementation

PropertyValue
Location Southbridge
Memory base address

  • GIC0: 0x1E000000

  • GIC1: 0x1E010000

  • GIC2: 0x1E020000

  • GIC3: 0x1E030000

Interrupt nFIQ and nIRQ signals are output to the Cortex-A8 and the tile site in response to an interrupt from a peripheral.
DMA−
Release versionCustom logic
Reference documentationSee Interrupts.

The four GICs implemented in the Southbridge are assigned as follows:

GIC0

generates Cortex-A8 nIRQ

GIC1

generates Cortex-A8 nFIQ

GIC2

generates tile site nIRQ

GIC3

generates tile site nFIQ

The GICs accept interrupts from peripherals in the Northbridge, Southbridge, on-board peripherals, and the tile site. The GICs generate nFIQ and nIRQ signals to the Cortex-A8 and the tile site. See Interrupts.

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