4.3.27. Test mode register, SYS_TESTMODE

This register at 0x100000FC provides Cortex-A8 test control and status.

Figure 4.25 shows the register bit assignment.

Figure 4.25. SYS_TESTMODE register

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The function of the register bits are listed in Table 4.29.

Table 4.29. SYS_TESTMODE register

BitsAccessNameResetDescription
[31:8]Read/Write0x000000Reserved.
[7:6]Read/Writeb00Reserved.
[5]Read/WriteTESTSTCFGCLKb0Test Input to the Cortex-A8 test chip. Must be set to 0 during normal functional operation.
[4]Read/WriteTESTSTCFGDENb0Test Input to the Cortex-A8 test chip. Must be set to 0 during normal functional operation.
[3]Read/WriteTESTSTCFGDINb0Test Input to the Cortex-A8 test chip. Must be set to 0 during normal functional operation.
[2]Read/WriteMBISTMODEb0Enables MBIST mode on the Cortex-A8 processor. Must be set to 0 during normal functional operation. See Cortex-A8 Technical Reference Manual (DDI 0344).
[1]Read/WritePLLSELECTb0Enables DFT clocking features of the PLL. Must be set to 0 to disable test circuitry during normal functional operation.
[0]Read/WriteTESTSELECTb0Scan test mode select. Controls TESTMODE on the Cortex-A8 processor. Must be set to 0 during normal functional operation. See Cortex-A8 Technical Reference Manual (DDI 0344).

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