4.3.18. PLD control register 1, SYS_PLD_CTRL1

The SYS_PLD_CTRL1 register at 0x10000074 sets the Config PLD write data register fields that configure the Cortex-A8 test chip.

Figure 4.18 shows the register bit assignment.

Figure 4.18. SYS_PLD_CTRL1 register

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The function of the register bits are listed in Table 4.20.

Table 4.20. SYS_PLD_CTRL1 register bit assignments

BitsAccessNameResetDescription
[31:15]Write ignored, read as zero0x0000Undefined
[14:13]Write ignored, read as zerob00Undefined
[12:11]Read/Write LockablePLLCLKTESTIPb10Selects which clock is output on the PLLCLKTESTOUT pin from the Cortex-A8 test chip (TP56 on PB-A8). Used for viewing internal PLL clocks during baseboard production test.
[10]Read/Write LockablePLLPOWERDNb0PLL control signal. Powers down the VCO in the PLL of the Cortex-A8 test chip.
[9]Read/Write LockablePLLBYPASSb0PLL control signal. Bypasses the PLL of the Cortex-A8 test chip. REFCLK drives all logic on the test chip when the PLL is in bypass mode.
[8]Read/Write LockableARESETNEONnb1NEON reset signal. Resets the NEON coprocessor of the Cortex-A8 test chip. This is an active LOW signal.
[7]Read/Write LockablenPORSETb1Active-LOW AXI reset input, that resets non-debug flops.
[6]Read/Write LockableARESETnb1AXI reset signal. Resets the AXI interface of the Cortex-A8 test chip. This is an active LOW signal.
[5]Read/Write LockablePLLRESETnb1Active-LOW hard reset input that resets the PLL.
[4]Read/Write LockableATRESETnb1ATB and CTI reset signal. Resets the ETM ATB interface, and the Cross Trigger Interface (CTI) of the Cortex-A8 test chip. This is an active LOW signal.
[3]Read/Write LockablePRESETnb1APB reset signal. Resets the Debug APB interface of the Cortex-A8 test chip. This is an active LOW signal.
[2]Read/Write LockableCFGNMFIb0Configures fast interrupts to be non-maskable:0 = clear the NMFI bit in the CP15 c1 Control Register1 = set the NMFI bit in the CP15 c1 Control Register.This pin is only sampled during reset of the processor. See the Cortex-A8 Technical Reference Manual (ARM DDI 0344).
[1]Read/Write LockableCP15DISABLEb0Disables CP15. See the Cortex-A8 Technical Reference Manual (ARM DDI 0344).
[0]Read/Write LockableVINITHIb0Controls the location of the exception vectors at reset:0 = start exception vectors at address 0x00000000 1 = start exception vectors at address 0xFFFF0000.This pin is only sampled during reset of the processor. See Cortex-A8 Technical Reference Manual (ARM DDI 0344).

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