4.3.15. DMA peripheral map register, SYS_DMAPSR

The DMA peripheral map register, SYS_DMAPSR at 0x10000064 permits the mapping of DMA channels to external interfaces. The register is set to zero by a reset. The DMA mapping is disabled by default.

Figure 4.15 shows the register bit assignment.

Figure 4.15. SYS_DMAPSR register

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The function of the register bits are listed in Table 4.16.

Table 4.16. SYS_DMAPSR register bit assignments

BitAccessNameResetDescription
[31:4]Write ignored, read as zero0x0000000Undefined
[3:2]Write ignored, read as zerob00Undefined
[1:0]Read/WriteDMAPSRb00

Selects the peripheral group to be mapped to DMA. See Table 4.17 for the bit encoding.


Table 4.17 lists the bit encoding. See Single Master Direct Memory Access Controller, SMDMAC for more information on the DMA logic.

Table 4.17. SYS_DMAPSR register bit coding

DMAPSR = b00DMAPSR = b01DMAPSR = b1XDMA Request and Response
PeripheralPeripheralPeripheralDMACSREQ DMACBREQ DMACCLR
reservedreservedreserved[15:8]
SCI TXUART0 TXreserved[7]
SCI RXUART0 RXreserved[6]
AACI RXUART1 TXreserved[5]
AACI TXUART1 RXreserved[4]
MCIUART2 TXreserved[3]
T1DMAC[0]UART2 RXreserved[2]
USB[1]SSP TXreserved[1]
USB[0]SSP RXreserved[0]

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