4.1. Memory map

The system memory map is divided with sections assigned to the Northbridge, Southbridge, and the Logic Tile site as shown in Table 4.1.

Table 4.1. System memory map

OwnerAddress rangeBus typeMemory region size
Northbridge

0x00000000- 0x0FFFFFFF

DMC256MB (DDR mirror)
Southbridge

0x10000000- 0x1001FFFF

APB128KB
Northbridge

0x10020000- 0x100DFFFF

AHB768KB
Northbridge

0x100E0000- 0x100FFFFF

APB128KB
Northbridge

0x10100000- 0x17FFFFFF

Reserved127MB
Southbridge

0x18000000- 0x1FFFFFFF

AHB128MB
Northbridge

0x20000000- 0x3FFFFFFF

Reserved512MB
Northbridge

0x40000000- 0x5FFFFFFF

SMC512MB
Northbridge

0x60000000- 0x6FFFFFFF

PCI256MB
Northbridge

0x70000000- 0x8FFFFFFF

DMC512MB
Northbridge

0x90000000- 0xBFFFFFFF

PCI768MB
Logic Tile site

0xC0000000- 0xFFFFFFFF

External1GB

Note

The 16MB memory region 0x00000000-0x00FFFFFF can be remapped to:

  • NOR flash (SMC CS0)

  • PISMO expansion memory (SMC CS4).

The other memory regions have fixed decoding and are handled either internally or externally.

The locations for memory, peripherals, and controllers for the Northbridge and the Southbridge are listed in Table 4.2.

Table 4.2. Memory map for standard peripherals

PeripheralAddress rangeBus typeRegion size

Dynamic memory mirror (0x70000000-0x7FFFFFFF)

During boot remapping however, the bottom 16MB of this memory region (0x00000000-0x00FFFFFF) can be:

  • NOR flash: 0x40000000-0x40FFFFFF

  • static expansion memory (PISMO): 0x50000000-0x50FFFFFF

0x00000000-0x0FFFFFFFAXI256MB
System registers0x10000000-0x10000FFFAPB4KB
System controller 00x10001000-0x10001FFFAPB4KB
3-Wire Serial Bus Control0x10002000-0x10002FFFAPB4KB
Reserved0x10003000-0x10003FFFAPB4KB
Advanced Audio CODEC0x10004000-0x10004FFFAPB4KB
MultiMedia Card Interface0x10005000-0x10005FFFAPB4KB
Keyboard/Mouse Interface 00x10006000-0x10006FFFAPB4KB
Keyboard/Mouse Interface 10x10007000-0x10007FFFAPB4KB
Reserved for future use0x10008000-0x10008FFFAPB4KB
UART 0 Interface

0x10009000-0x10009FFF

APB4KB
UART 1 Interface

0x1000A000-0x1000AFFF

APB4KB
UART 2 Interface

0x1000B000-0x1000BFFF

APB4KB
UART 3 Interface

0x1000C000-0x1000CFFF

APB4KB
Synchronous Serial Port Interface

0x1000D000-0x1000DFFF

APB4KB
Smart Card Interface0x1000E000-0x1000EFFFAPB4KB
Watchdog 0 Interface0x1000F000-0x1000FFFFAPB4KB

Watchdog 1 Interface

0x10010000-0x10010FFF

APB4KB

Timer modules 0 and 1 Interface

(Timer 1 registers start at 0x10011020)

0x10011000-0x10011FFF

APB4KB

Timer modules 2 and 3 Interface

(Timer 3 registers start at 0x10012020)

0x10012000-0x10012FFF

APB4KB

GPIO Interface 0

0x10013000-0x10013FFF

APB4KB

GPIO Interface 1

0x10014000-0x10014FFF

APB4KB

GPIO Interface 2 (miscellaneous onboard I/O)

0x10015000-0x10015FFF

APB4KB
Serial Bus Control (DVI)

0x10016000-0x10016FFF

APB4KB

Real Time Clock Interface

0x10017000-0x10017FFF

APB4KB
Timer Modules 4 and 5 Interface (Timer 5 registers start at 0x10018020)

0x10018000-0x10018FFF

APB4KB
Timer Modules 6 and 7 Interface (Timer 7 registers start at 0x10019020)0x10019000-0x10019FFFAPB4KB
System Controller 10x1001A000-0x1001AFFFAPB4KB
Reserved for future use (4K x 5)0x1001B000-0x1001FFFFAPB20KB

Color LCD Controller configuration

0x10020000-0x1002FFFFAHB64KB

DMA Controller configuration

0x10030000-0x1003FFFFAHB64KB
Reserved (64K x 2)0x10040000-0x1005FFFFAHB128KB
Internal Northbridge SRAM0x10060000-0x1007FFFFAXI128KB
Reserved (64K x 6)0x10080000-0x100DFFFFAHB384KB
Dynamic Memory Controller configuration

0x100E0000-0x100E0FFF

APB4KB
Static Memory Controller configuration0x100E1000-0x100E1FFFAPB4KB
Reserved

0x100E2000-0x100E2FFF

APB4KB
APB Registers (PLL configuration)

0x100E3000-0x100E3FFF

APB4KB
Reserved for future use

0x100E4000-0x100EFFFF

APB48KB
Reserved for future use

0x100F0000-0x100FFFFF

APB64KB
Reserved

0x10100000-0x103FFFFF

3MB
Reserved for future use

0x10400000-0x16FFFFFF

AHB or AXI108MB
Reserved for future use

0x17000000-0x17FFFFFF

AXI16MB
Compact Flash

0x18000000-0x18000FFF

AHB4KB
Reserved for future use

0x18001000-0x1BFFFFFF

AHB63.096MB
DAP ROM table

0x1C000000-0x1DFFFFFF

AHB32MB
Generic Interrupt Controller 1 (GIC1) (nIRQ interrupt handling for Cortex-A8)

0x1E000000-0x1E00FFFF

APB64KB
Generic Interrupt Controller 2 (GIC2) (nFIQ interrupt handling for Cortex-A8)

0x1E010000-0x1E01FFFF

APB64KB
Generic Interrupt Controller 3 (GIC3) (nIRQ interrupt handling for Tile Site)

0x1E020000-0x1E02FFFF

APB64KB
Generic Interrupt Controller 4 (GIC4) (nFIQ interrupt handling for Tile Site)

0x1E030000-0x1E03FFFF

APB64KB
Reserved for future use

0x1E040000-0x1EFFFFFF

AHB15.75MB
Reserved for future use

0x1F000000-0x1FFFFFFF

AHB16MB
Reserved

0x20000000-0x3FFFFFFF

AHB or AXI512MB

SMC Chip Selects:

  • CS0 NOR flash 0x40000000-0x43FFFFFF

  • CS1 NOR flash 0x44000000-0x47FFFFFF

  • CS2 Cellular RAM 0x48000000-0x4BFFFFFF

  • CS3 configuration PLD

    Config flash 0x4C000000-0x4DFFFFFF

    Ethernet 0x4E000000-0x4EFFFFFF

    USB 0x4F000000-0x4FFFFFFF

  • CS4 PISMO (nCS0) 0x50000000-0x53FFFFFF

  • CS5 PISMO (nCS1) 0x54000000-0x57FFFFFF

  • CS6 PISMO (nCS2) 0x58000000-0x5BFFFFFF

  • CS7 PISMO (nCS3) 0x5C000000-0x5FFFFFFF

0x40000000-0x5FFFFFFF

SMC512MB

PCI interface

0x60000000-0x6FFFFFFF

PCI256MB
Dynamic memory (CS0)

0x70000000-0x7FFFFFFF

DDR256MB
Dynamic memory (CS1)

0x80000000-0x8FFFFFFF

DDR256MB

PCI interface

0x90000000-0xBFFFFFFF

PCI768MB
Logic Tile site expansion. (If a Logic tile is not fitted, the baseboard aborts accesses to this memory region)

0xC0000000-0xFFFFFFFF

External1GB

Figure 4.1 shows an overview of the memory map.

Figure 4.1. System memory map

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