4.3.16. PCI Express status register, SYS_PEX_STAT

The PCI express status register, SYS_PEX_STAT at 0x10000068 monitors the lane status of the PCI-X to PCI Express bridge (PEX8114) and PCI Express switch (PEX 8518) components.

Figure 4.16 shows the register bit assignment.

Figure 4.16. SYS_PEX_STAT register

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The function of the register bits are listed in Table 4.18.

Table 4.18. SYS_PEX_STAT register bit assignments

[31:16]Write ignored, read as zero0x0000Undefined
[15:12]Read-onlyPEX8114 PEX_LANE_GOOD0xXPCI-X to PCI Express bridge lane status
[11:0]Read-onlyPEX8518 PEX_LANE_GOOD0xXXXPCI Express switch lane status


The PEX_LANE_GOOD signals indicate the presence and link-up state of each PCI Express lane. These determine which lanes are active, and provide the status of the final negotiated link width as follows:

  • if the PEX_LANE_GOODx signal is continuously active, the link is trained to its programmed width

  • if the PEX_LANE_GOODx signal alternates to and from the active state, the link is trained with fewer lanes than the programmed width.

Please refer to the PEX 8114 and PEX 8518 technical documentation at the PLX Technology Inc website: www.plxtech.com for further details.

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