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The PL111 PrimeCell Color LCD Controller (CLCDC)
is an AMBA compliant SoC peripheral that is developed,
tested, and licensed by ARM Limited.
Table 4.36. CLCDC implementation
| Property | Value |
|---|---|
| Location | Northbridge |
| Memory base address |
NoteThere is also a LCD system control register at |
| Interrupt | 55 |
| DMA | − |
| Release version | ARM CLCDC PL111 (version r0p0) |
| Reference documentation | ARM PrimeCell Color LCD Controller (PL111) Technical Reference Manual DDI 0293. |
The following locations are reserved, and must not be used during normal operation:
locations at offsets 0x030 to 0x1FE are
reserved for possible future extensions
locations at offsets 0x400 to 0x7FF are
reserved for test purposes.
Different display resolutions require different data and synchronization timing. OSCCLK4 (25MHz default) is assigned as CLCDCLK for the LCD controller. Default display resolution is 1024x768 at 60Hz frame rate. See PrimeCell Color LCD Controller (PL111) Technical Reference Manual (DDI 0293) for details of the LCD timing registers.
| Copyright © 2008-2011 ARM Limited. All rights reserved. | ARM DUI 0417D |
| PDF version | |
| Home > Programmer’s Reference > Color LCD Controller, CLCDC |