4.3.19. PLD control register 2, SYS_PLD_CTRL2

The SYS_PLD_CTRL2 register at 0x10000078 reads the PLD read data register fields that provide status on the Cortex-A8 test chip and the PLD.

Figure 4.19 shows the register bit assignment.

Figure 4.19. SYS_PLD_CTRL2 register

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The function of the register bits are listed in Table 4.21.

Table 4.21. SYS_PLD_CTRL2 register bit assignments

BitsAccessNameResetDescription
[31:8]Read as zero, write ignored.0x000000

Undefined

[7]Read-onlyCOMMRXb0

Comms channel receive.

[6]Read-onlyCOMMTXb0

Comms channel transmit.

[5]Read-onlySTANDBYWFIb0

WFI indicator. Indicates if the Cortex-A8 processor and the AXI interface are in idle state.

See the Cortex-A8 Technical Reference Manual (ARM DDI 0344).

[4]Read -onlyPLL_LOCKb0

PLL locked indicator. Indicates when the Cortex-A8 test chip and onboard PLLs are locked.

[3:0]Read-onlyPLDID0x0

PLD identifier. Provides PLD build information.


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