4.11.2. Generic interrupt controller registers

This section describes the GIC programming registers.

Memory map

To access a GIC register, use the base address for the specific GIC listed in Table 4.45 together with the offset value for the specific CPU interface register listed in Table 4.46 or the specific Distributor register listed in Table 4.55.

Table 4.45. Interrupt control register addresses

RegistersBase Address
PB-A8 GIC0 CPU interface registers0x1E000000
PB-A8 GIC0 distributor registers0x1E001000
PB-A8 GIC1 CPU interface registers0x1E010000
PB-A8 GIC1 distributor registers0x1E011000
PB-A8 GIC2 CPU interface registers0x1E020000
PB-A8 GIC2 distributor registers0x1E021000
PB-A8 GIC3 CPU interface registers0x1E030000
PB-A8 GIC3 distributor registers0x1E031000

CPU Interface registers

The CPU interface registers address offset values are listed in Table 4.46.

Table 4.46. CPU interface registers address offset values

RegisterOffset Address
CPU control0x000
Priority mask0x004
Binary point0x008
Interrupt acknowledge0x00C
End of interrupt0x010
Running interrupt0x014
Highest pending interrupt0x018

CPU control register

The CPU control register is shown in Figure 4.28.

Figure 4.28. CPU control register

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The function of the register bits are listed in Table 4.47.

Table 4.47. CPU control register

BitsAccessNameResetDescription
[31:4]Write ignored, read as zero0x0000000Reserved
[3:2]Write ignored, read as zerob00 
[0]Read/WriteEnableb0b0 = disable the CPU interface for this GIC b1 = enable the CPU interface for this GIC

Priority mask register

The Priority mask register is shown in Figure 4.29.

Figure 4.29. Priority mask register

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The function of the register bits are listed in Table 4.48.

Table 4.48. Priority mask

BitsAccessNameResetDescription
[31:8]Write ignored, read as zero0x000000Reserved
[7:4]Read/WritePriority mask0x0The Priority mask is used to prevent interrupts from being sent to the processor. The CPU Interface asserts an an interrupt request if the priority of the highest pending interrupt sent by the Distributor is greater than the priority set in the Priority mask field. For example: 0x0 means all interrupts are masked. A Priority mask value of 0xF means interrupts with priority 0xF are masked but interrupts with higher priority values 0x0 to 0xE are not masked.
[3:0]Write ignored, read as zero0x0Reserved

Binary point register

The Binary point register is shown in Figure 4.30.

Figure 4.30. Binary point register

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The function of the register bits are listed in Table 4.49.

Table 4.49. Binary point

BitsAccessNameResetDescription
[31:4]Write ignored, read as zero0x0000000Reserved
[3]Write ignored, read as zerob0Reserved
[2:0]Read/WriteBinary pointb011Sets the position of a ‘binary point’ that controls which bits of an interrupt’s priority are compared for pre-emption purposes. This allows software to adjust the level of interrupt pre-emption in the system.

The Binary point register bit assignments are listed in Table 4.50.

Table 4.50. Binary Point bit values assignment

Bit valueMeaning
b011All priority bits are compared for pre-emption
b100Only bits [7:5] of priority are compared for pre-emption
b101Only bits [7:6] of priority are compared for pre-emption
b110Only bit [7] of priority is compared for pre-emption
b111No pre-emption is performed

Note

Writing a value not listed in Table 4.50 has the same effect as writing b011.

An example of Binary point register operation is shown in Figure 4.31.

Figure 4.31. Binary point example

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In this example there are three interrupts A, B, C that use 4 priority bits, and the Binary point register is set to 0x00000005 so the binary point is set between bit-6 and bit-5.

Zero (b0000) is the highest priority, so A is a higher priority interrupt than B and C. For pre-emption, any bits to the right of the binary point are ignored, so A can interrupt B or C, but B cannot interrupt C.

If interrupt A is active and interrupts B and C are pending, when A has completed B will be taken as it has a higher priority than C.

Interrupt acknowledge

The Interrupt acknowledge register is shown in Figure 4.32.

Figure 4.32. Interrupt acknowledge register

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The function of the register bits are listed in Table 4.51.

Table 4.51. Interrupt acknowledge

BitsAccessNameResetDescription
[31:16]Write ignored, read as zero0x0000Reserved
[15:13]Write ignored, read as zerob00Reserved
[12:10]Read-onlyCPU source IDb000Reserved for multi-processor use
[9:0]Read-onlyInterrupt IDb1111111111The processor acquires the interrupt number by reading this register from the interrupting GIC. Pre-empted interrupts are recorded as active.

Note

In the event that interrupt priorities are changed before the processor reads the interrupt number, and the interrupt has become a lower priority, the interrupt number returned is 1023 to indicate a spurious interrupt.

End of interrupt

The End of interrupt register is shown in Figure 4.33.

Figure 4.33. End of interrupt register

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The function of the register bits are listed in Table 4.52.

Table 4.52. End of interrupt

BitsAccessNameResetDescription
[31:13]WriteIgnoredReserved
[12:10]Write-onlyCPU source IDReserved for multi-processor use
[9:0]Write-onlyInterrupt IDWhen the interrupt has been completed by the processor, it writes the interrupt number to this register in the interrupting GIC.

Running interrupt

The Running interrupt register is shown in Figure 4.34.

Figure 4.34. Running interrupt register

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The function of the register bits are listed in Table 4.53.

Table 4.53. Running interrupt

BitsAccessNameResetDescription
[31:8]Read-only0x000000Reserved
[7:4]Read-onlyPriority0xFContains the priority level of the currently running interrupt.
[3:0]Read-only0x0Reserved

Highest pending interrupt

The Highest pending interrupt register is shown in Figure 4.35.

Figure 4.35. Highest pending interrupt register

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The function of the register bits are listed in Table 4.54.

Table 4.54. Highest pending interrupt

BitsAccessNameResetDescription
[31:16]Write ignored, read as zero0x0000Reserved
[15:13]Write ignored, read as zerob000Reserved
[12:10]Read-onlyCPU source IDb000Reserved for multi-processor use
[9:0]Read-onlyInterrupt IDb1111111111The processor acquires the interrupt number of the highest pending interrupt being presented to the CPU Interface by the Distributor. If no interrupt is Pending then the Interrupt ID returned is1023, indicating a spurious interrupt.

Distribution registers

The Distribution registers address offset values are listed in Table 4.55. See Table 4.45 for each GICs Distributor base address.

Table 4.55. Distribution registers address offset values

Distribution RegisterOffset Address
Distributor control0x000
Controller type0x004
Reserved0x0080x0FC
Set-enable0 [a]0x100
Set-enable10x104
Set-enable20x108
Reserved0x10C0x17C
Clear-enable0 [a]0x180
Clear-enable10x184
Clear-enable20x188
Reserved0x18C0x1FC
Set-pending0 [a]0x200
Set-pending10x204
Set-pending20x208
Reserved0x20C0x27C
Clear-pending0 [a]0x280
Clear-pending10x284
Clear-pending20x288
Reserved0x28C0x2FC
Active0 [a]0x300
Active10x304
Active20x308
Reserved0x30C0x3FC
Priority0x4000x45C
Reserved0x4600x7FC
CPU targets0x8000x85C
Reserved0x8600xBFC
Configuration0xC000xC14
Reserved0xC18EFC
Software interrupt0xF00
Reserved0xF040xFFC

[a] Private on PB-A8.


Distributor control register

The Distributor control register is shown in Figure 4.36.

Figure 4.36. Distributor control register

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The function of the register bits are listed in Table 4.56.

Table 4.56. Distributor control

BitsAccessNameResetDescription
[31:4]Write ignored, read as zero0x0000000Reserved
[3:2]Write ignored, read as zerob00Reserved
[0]Read/WriteEnableb0b0 = interrupts are disable for this GIC b1 = interrupts are enabled for this GIC

Controller type register

The Controller type register is shown in Figure 4.37.

Figure 4.37. Controller type register

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The function of the register bits are listed in Table 4.57.

Table 4.57. Controller type

BitsAccessNameResetDescription
[31:8]Write ignored, read as zero0x000000Reserved
[7:5]Read-onlyCPU numberb000Fixed value indicating a single CPU is serviced by this GIC.
[4:0]Read-onlyID lines numberb00010Fixed value indicating 64 external interrupt input lines are available for this GIC.

Set-enable0 register

The Set-enable0 register at address offset 0x100 is reserved for private use in the PB-A8.

Set-enable1 register

The Set-enable1 register is shown in Figure 4.38.

Figure 4.38. Set-enable1 register

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The function of the register bits are listed in Table 4.58.

Table 4.58. Set-enable1

BitsAccessNameResetDescription
[31:0]Read/WriteInterrupt Enable0x00000000Read this register to determine which interrupts are enabled. Bits 0 to 31 correspond to PB-A8 interrupt input lines 32 to 63 respectively. A bit set to 1 indicates an enabled interrupt. Write a 1 to a bit to enable the corresponding interrupt. Use Read-Modify-Write to maintain reserved interrupt states. See Table 4.44 for details of the PB-A8 external interrupt sources.

Note

There are a number of PB-A8 reserved interrupt input lines that should not be enabled using the Set-enable1 register as the result will be unpredictable. Table 4.59 lists the PB-A8 reserved interrupt input lines for the corresponding Set-enable1 register bit.

Table 4.59. Reserved interrupts

Set-enable1BitReserved Interrupt
[2]34
[3]35
[9]41
[22]54
[25]57
[27]59
[30]62
[31]63

Set-enable2 register

The Set-enable2 register is shown in Figure 4.39.

Figure 4.39. Set-enable2

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The function of the register bits are listed in Table 4.60.

Table 4.60. Set-enable2

BitsAccessNameResetDescription
[31:0]Read/WriteInterrupt Enable0x00000000Read this register to determine which interrupts are enabled. Bits 0 to 31 correspond to PB-A8 interrupt input lines 64 to 95 respectively. A bit set to 1 indicates an enabled interrupt. Write a 1 to a bit to enable the corresponding interrupt. Use Read-Modify-Write to maintain reserved interrupt states. See Table 4.44 for details of the PB-A8 external interrupt sources.

Note

There are a number of PB-A8 reserved interrupt input lines that should not be enabled using the Set-enable2 register as the result will be unpredictable. Table 4.61 lists the PB-A8 reserved interrupt input lines for the corresponding Set-enable2 register bit.

Table 4.61. Reserved interrupts

Set-enable2 BitReserved Interrupt
[11]75
[12]76
[13]77
[14]78

Clear-enable0 register

The Clear-enable0 register at address offset 0x180 is reserved for private use in the PB-A8.

Clear-enable1 register

The Clear-enable1 register is shown in Figure 4.40.

Figure 4.40. Clear-enable1 register

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The function of the register bits are listed in Table 4.62.

Table 4.62. Clear-enable1

BitsAccessNameResetDescription
[31:0]Read/WriteInterrupt Enable0x00000000Read this register to determine which interrupts are cleared. Bits 0 to 31 correspond to PB-A8 interrupt input lines 32 to 63 respectively. A bit set to 0 indicates a cleared interrupt. Write a 1 to a bit to clear the corresponding interrupt. Use Read-Modify-Write to maintain reserved interrupt states. See Table 4.44 for details of the PB-A8 external interrupt sources.

Clear-enable2 register

The Clear-enable2 register is shown in Figure 4.41.

Figure 4.41. Clear-enable2 register

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The function of the register bits are listed in Table 4.63.

Table 4.63. Clear-enable2

BitsAccessNameResetDescription
[31:0]Read/WriteInterrupt Enable0x00000000Read this register to determine which interrupts are cleared. Bits 0 to 31 correspond to PB-A8 interrupt input lines 64 to 95 respectively. A bit set to 0 indicates a cleared interrupt. Write a 1 to a bit to clear the corresponding interrupt. Use Read-Modify-Write to maintain reserved interrupt states. See Table 4.44 for details of the PB-A8 external interrupt sources.

Set-pending0 register

The Set-pending0 register at address offset 0x200 is reserved for private use in the PB-A8.

Set-pending1 register

The Set-pending1 register is shown in Figure 4.42.

Figure 4.42. Set-pending1 register

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The function of the register bits are listed in Table 4.64.

Table 4.64. Set-pending1

BitsAccessNameResetDescription
[31:0]Read/WriteInterrupt Pending0x00000000Read this register to determine which interrupts are pending. Bits 0 to 31 correspond to PB-A8 interrupt input lines 32 to 63 respectively. A bit set to 1 indicates a pending interrupt. Write a 1 to a bit to set the corresponding interrupt into Pending state. Use Read-Modify-Write to maintain reserved interrupt states. See Table 4.44 for details of the PB-A8 external interrupt sources.

Set-pending2 register

The Set-pending2 register is shown in Figure 4.43.

Figure 4.43. Set-pending2 register

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The function of the register bits are listed in Table 4.65.

Table 4.65. Set-pending2

BitsAccessNameResetDescription
[31:0]Read/WriteInterrupt Pending0x00000000Read this register to determine which interrupts are pending. Bits 0 to 31 correspond to PB-A8 interrupt input lines 64 to 95 respectively. A bit set to 1 indicates a pending interrupt. Write a 1 to a bit to set the corresponding interrupt into Pending state. Use Read-Modify-Write to maintain reserved interrupt states. See Table 4.44 for details of the PB-A8 external interrupt sources.

Clear-pending0 register

The Clear-pending0 register at address offset 0x280 is reserved for private use in the PB-A8.

Clear-pending1 register

The Clear-pending1 register is shown in Figure 4.44.

Figure 4.44. Clear-pending1 register

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The function of the register bits are listed in Table 4.66.

Table 4.66. Clear-pending1

BitsAccessNameResetDescription
[31:0]Read/WriteInterrupt Pending0x00000000Read this register to determine which interrupts are pending. Bits 0 to 31 correspond to PB-A8 interrupt input lines 32 to 63 respectively. A bit set to 1 indicates a pending interrupt. Write a 1 to a bit to set the corresponding interrupt into the Inactive state. Use Read-Modify-Write to maintain reserved interrupt states. See Table 4.44 for details of the PB-A8 external interrupt sources.

Clear-pending2 register

The Clear-pending2 register is shown in Figure 4.45.

Figure 4.45. Clear-pending2 register

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The function of the register bits are listed in Table 4.67.

Table 4.67. Clear-pending2

BitsAccessNameResetDescription
[31:0]Read/WriteInterrupt Pending0x00000000Read this register to determine which interrupts are pending. Bits 0 to 31 correspond to PB-A8 interrupt input lines 64 to 95 respectively. A bit set to 1 indicates a pending interrupt. Write a 1 to a bit to set the corresponding interrupt into the Inactive state. Use Read-Modify-Write to maintain reserved interrupt states. See Table 4.44 for details of the PB-A8 external interrupt sources.

Active0 register

The Active0 register at address offset 0x300 is reserved for private use in the PB-A8.

Active1 register

The Active1 register is shown in Figure 4.46.

Figure 4.46. Active1 register

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The function of the register bits are listed in Table 4.68.

Table 4.68. Active1

BitsAccessNameResetDescription
[31:0]Read-onlyInterrupt Active0x00000000Read this register to determine which interrupts are active. Bits 0 to 31 correspond to PB-A8 interrupt input lines 32 to 63 respectively. A bit set to 1 indicates an interrupt is in the Active state. See Table 4.44 for details of the PB-A8 external interrupt sources.

Active2 register

The Active2 register is shown in Figure 4.47.

Figure 4.47. Active2 register

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The function of the register bits are listed in Table 4.69.

Table 4.69. Active2

BitsAccessNameResetDescription
[31:0]Read-onlyInterrupt Active0x00000000Read this register to determine which interrupts are active. Bits 0 to 31 correspond to PB-A8 interrupt input lines 64 to 95 respectively. A bit set to 1 indicates an interrupt is in the Active state. See Table 4.44 for details of the PB-A8 external interrupt sources.

Priority registers

There are 24 Priority registers. Each register holds the priority level for 4 interrupt IDs. Priority registers 0 to 7 at address offsets 0x400 to 0x41C are reserved for Interrupt IDs 0 to 31 that are for private use in the PB-A8. Priority registers 8 to 23 at address offsets 0x420 to 0x45C hold priority levels for Interrupt IDs 32 to 95 respectively. Priority registers 8 to 23 address offsets and Interrupt IDs are listed in Table 4.70.

Table 4.70. Priority register address offsets and Interrupt IDs

Priority RegisterAddress OffsetInterrupt ID
Priority80x420ID32 − ID35
Priority90x424ID36 − ID39
Priority100x428ID40 − ID43
Priority110x42CID44 − ID47
Priority120x430ID48− ID51
Priority130x434ID52 − ID55
Priority140x438ID56− ID59
Priority150x43CID60 − ID63
Priority160x440ID64 − ID67
Priority170x444ID68 − ID71
Priority180x448ID72 − ID75
Priority190x44CID76 − ID79
Priority200x450ID80 − ID83
Priority210x454ID84 − ID87
Priority220x458ID88 − ID91
Priority230x45CID92 − ID95

The Priority register fields are shown in Figure 4.48.

Figure 4.48. Priority register

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Note

Priority is a 4-bit number where zero is the highest priority. Future implementations of the GIC may use 8-bits for priority so the priority is stored in the most significant bits of an 8-bit field.

Each 32-bit register holds the priority for 4 interrupts. For example, interrupt ID 32 − 35 are stored in Priority8 register at address offset 0x420:

  • Interrupt ID 32 is stored in bits [7:4], bits 3:0 are unused and set to zero

  • Interrupt ID 33 is stored in bits [15:12], bits [11:8] are unused and set to zero

  • Interrupt ID 34 is stored in bits [23:20], bits [19:16] are unused and set to zero

  • Interrupt ID 35 is stored in bits [31:28], bits [27:24] are unused and set to zero.

CPU targets registers

There are 24 CPU targets registers. Each register holds the target CPU data for 4 interrupt IDs. CPU targets registers 0 to 7 at address offsets 0x800 to 0x81C are reserved for Interrupt IDs 0 to 31 that are for private use in the PB-A8. CPU targets registers 8 to 23 at address offsets 0x820 to 0x85C hold CPU targets data for Interrupt IDs 32 to 95 respectively. CPU targets registers 8 to 23 address offsets and Interrupt IDs are listed in Table 4.71.

Table 4.71. CPU targets register address offsets and Interrupt IDs

Priority RegisterAddress OffsetInterrupt ID
CPUtargets80x820ID32 − ID35
CPUtargets90x824ID36 − ID39
CPUtargets100x828ID40 − ID43
CPUtargets110x82CID44 − ID47
CPUtargets120x830ID48− ID51
CPUtargets130x834ID52 − ID55
CPUtargets140x838ID56− ID59
CPUtargets150x83CID60 − ID63
CPUtargets160x840ID64 − ID67
CPUtargets170x844ID68 − ID71
CPUtargets180x848ID72 − ID75
CPUtargets190x84CID76 − ID79
CPUtargets200x850ID80 − ID83
CPUtargets210x854ID84 − ID87
CPUtargets220x858ID88 − ID91
CPUtargets230x85CID92 − ID95

The CPU targets register fields are shown in Figure 4.49.

Figure 4.49. CPU targets register

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Each register can store a bit-map for 4 Interrupt IDs x 4 CPUs. The GICs in the PB-A8 have been implemented for one target CPU (CPU 0) so the CPU target registers are initialized to 0x01010101.

Configuration register

There are 6 Configuration registers. Each register holds the configuration data for 16 interrupt IDs. Configuration registers 0 and 1 at address offsets 0xC00 and 0xC04 are reserved for Interrupt IDs 0 to 31 that are for private use in the PB-A8. Configuration registers 2 to 5 at address offsets 0xC08 to 0xC14 hold configuration data for Interrupt IDs 32 to 95 respectively. Configuration registers 2 to 5 address offsets and Interrupt IDs are listed in Table 4.72.

Table 4.72. Configuration register address offsets

Configuration registerAddress OffsetInterrupt IDs
Configuration20xC08ID32 − ID47
Configuration30xC0CID48 − ID63
Configuration40xC10ID64 − ID79
Configuration50xC14ID80 − ID95

The Configuration register fields are shown in Figure 4.50.

Figure 4.50. Configuration register

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The Interrupt Configuration registers have 2 bits IDn[1:0] for each interrupt ID n. These two bits set each interrupt to be level or edge sensitive, and determine which software model is used:

1-N model

Only one CPU takes the interrupt. An interrupt that is taken up by any CPU clears the pending status on all CPUs. This is the only model available for the PB-A8 GIC implementation as there is a single CPU.

N-N model

This model has been deprecated and should not be used.

For example, for Interrupt ID 32 set bits [1:0] of Configuration2 register at address offset 0xC08 to b01 for level-sensitive or b11 for edge sensitive. The default is all interrupts are level-sensitive, set by the Boot Monitor writing 0x55555555 to the Configuration registers.

Software interrupt register

This is a write-only register. Write to this register to trigger an interrupt ID32 − ID95.

The Software interrupt register fields are shown in Figure 4.51.

Figure 4.51. Software interrupt register

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The function of the register bits are listed in Table 4.73.

Caution

If you attempt to trigger an interrupt with an ID larger than the number of supported interrupts, or that references a CPU that is not present, there can be unpredictable results in the Distributor.

Table 4.73. Software interrupt

BitsAccessNameResetDescription
[31:26]Write-onlyReserved
[25:24]Write-onlyTarget list filter

The filter options are: 00: Interrupt sent to CPUs listed in CPU target list. 01: CPU target list is ignored, interrupt is sent to all but the requesting CPU. 10: CPU target list is ignored, interrupt is sent to the requesting CPU only. 11: Reserved. Valid entries for the PB-A8 are: b00 if CPU target list = b00000001 b10 otherwise.

[23:16]Write-onlyCPU target listThere can be up to 8 CPU targets. PB-A8 has 1 CPU target only. Valid entry is: b00000001 (CPU0)
[15:10]Write-onlyReserved
[9:0]Write-onlyInterrupt IDID of interrupt to be triggered. Valid range for the PB-A8 is ID32 to ID95: b0000100000 to b0001011111

For example, write 0x02000021 to the PB-A8 Software interrupt register to trigger Interrupt ID 33. Bits [9:0] contain the interrupt ID, bits [25:24] are set to b10 to ignore the list of CPU targets in bits [23:16]. The remaining bits should be set to zero. You should see the Set-pending1 register at offset 0x204 set to 0x00000002.

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