4.3.28. PLL Reset register, SYS_PLL_RESET

This register at 0x10000100 sets the Cortex-A8 test chip PLL hardware reset values.

Figure 4.26 shows the register bit assignment.

Figure 4.26. SYS_PLL_RESET register

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The function of the register bits are listed in Table 4.30.

Table 4.30. SYS_PLL_RESET register

BitsAccessNameResetDescription
[31:24]Read/Write LockablePLLADIV0x0BAXICLK divider value (ADIV[7:0]) when TESTSELECT = 0. See PLL for divider details and Test mode register, SYS_TESTMODE for details on controlling TESTSELECT.
[23:16]Read/Write LockablePLLODIV0x01CLK divider value (ODIV[7:0]) when TESTSELECT = 0. See PLL for divider details and Test mode register, SYS_TESTMODE for details on controlling TESTSELECT.
[15:4]Read/Write LockablePLLFBDIV0x01DPLL multiplication factor (FBDIV[11:0]). See PLL for divider details.
[3:0]Read/Write LockablePLLREFDIV0x0Reference clock (REFCLK) divider value (NDIV[3:0]). See PLL for divider details.

Copyright © 2008-2011 ARM Limited. All rights reserved.ARM DUI 0417D