B.2.1. Clock frequency restrictions

The maximum tile site clock (TSCLK) frequency that can be used for reliable operation depends on the type of Logic Tile fitted. The default frequency setting is 25MHz and assumes that a LTXC2V8000 is to be used.


The eight ICS307 programmable oscillators (OSC0 − OSC7) can be programmed to deliver very high frequency clock signals (200MHZ). The settings for VCO divider, output divider, and output select values are interrelated and must be set correctly. Some combinations of settings do not result in stable operation. For more information on the ICS clock generator and a frequency calculator, see the IDT web site: www.idt.com.

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