B.2.2. AXI bus timings

Table B.2 lists the tile site multiplexed AXI bus timings.

Table B.2. AC Specifications

Clock CycletTScyc22.2nsCmax=15pF
Output valid time after clock edgetTSov9.92ns 
Output hold time after clock edgetTSoh0.99ns 
Input setup time to clock edgetTSis7.38ns 
Input hold time after clock edgetTSih0.88ns 

Figure B.1 shows the tile site multiplexed AXI timing diagram.

Figure B.1. Tile site multiplexed AXI timing

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