D.2.2. RealView Logic Tile clock

The PB-A8 provides an individually buffered tile site clock TSCLK at the HDRZ connector on CLK_OUT_PLUS1 (pin 140) and CLK_OUT_PLUS2 (pin 142). The default frequency for TSCLK is 25MHz and is set by OSCCLK2 on the PB-A8. TSCLK is also supplied to the Northbridge async bridges to synchronize AXI signals to and from the tile site.

Note

The remaining RealView Logic Tile clock sources are not used. Ensure that your RealView Logic Tile configuration is compatible with the available clock sources. See Clock architecture for more information on PB-A8 clock routing.

Copyright © 2008-2011 ARM Limited. All rights reserved.ARM DUI 0417D