D.2.5. Reset

A user design in a RealView Logic Tile can reset the baseboard by driving the nSRST signal LOW. This has the same effect as pressing the Soft Reset push-button and forces the reset controller to the level specified by the SYS_RESETCTRL register RESETCTRL field. See Reset Control Register, SYS_RESETCTL for details.

nSRST is synchronized by the reset controller and can be driven from any clock source. It must, however, be driven active for a minimum of 84ns (two cycles of 24MHz) to ensure that it is sampled by the reset controller. In order to avoid a deadlock condition, the user design must stop driving the nSRST signal after nSYSRST is asserted.

nSRST is active low and open-drain. It is shared with the JTAG interface and must not be driven to HIGH state. A resistor on the baseboard pulls the signal HIGH.

The RealView Logic Tile also uses the nPORESET signal to generate a local D_nTRST pulse.

The GLOBAL_DONE signal is held LOW until the FPGA on the RealView Logic Tile has finished configuration. The system is held in reset until this signal goes HIGH.

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