3.3.1. Cortex-A8 test chip overview

Figure 3.6 shows the top-level functionality of the test chip.

Figure 3.6. top-level view of Cortex-A8 test chip

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Note

On the PB-A8, the test chip is tightly coupled to the Debug FPGA to implement CoreSight™ technology for system trace and debug. See Debug FPGA.

Cortex-A8 processor

For details on the Cortex-A8 processor components see Cortex-A8 Technical Reference Manual (ARM DDI 0344).

PLL

The PLL includes a Voltage Controlled Oscillator (VCO) and digital circuitry. Either the PLL or an external reference clock provides the timing required by the Cortex-A8 test chip.

Boundary Scan TAP

An IEEE 1149.1 TAP controller provides and controls the test chip boundary scan chain. This TAP controller is required by ARM during reconfiguration of the PB-A8. It is not required for normal configuration or debug of the PB-A8. It uses the same test chip IEEE 1149.1 pins for JTAG communications to keep the number of additional pins required to a minimum.

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