3.6.4. APB peripherals

The majority of the controllers and interfaces implemented in the Southbridge are standard ARM PrimeCell® components:

Advanced Audio CODEC Interface, AACI

The ARM PrimeCell Advanced Audio CODEC Interface (AACI) PL041 is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB).

The PrimeCell AACI provides communication to an off-chip CODEC (LM4549) that supports the AC-link protocol.

See Advanced Audio CODEC Interface, AACI for details of PB-A8 usage and the ARM PrimeCell Advanced Audio CODEC Interface (PL041) Technical Reference Manual (ARM DDI 0173) for full programming details. The physical interface provided by the PB-A8 is shown in Audio CODEC interface.

Multimedia Card Interface, MCI

The ARM PrimeCell Multimedia Card Interface (MCI) PL180 is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB).

The PrimeCell MCI provides all functions specific to the multimedia and secure digital memory card such as the clock generation unit, power management control, and command a data transfer. The interface conforms to Multimedia Card Specification v2.11 and Secure Digital Memory Card Physical Layer Specification v0.96.

See MultiMedia Card Interface, MCI for details of PB-A8 usage and the ARM PrimeCell Multimedia Card Interface (PL180) Technical Reference Manual (ARM DDI 0172) for full programming details. The physical interface provided by the PB-A8 is shown in MMC and SD card interface.

Keyboard and Mouse Interface, KMI

The ARM PrimeCell PS2 Keyboard/Mouse Interface (KMI) PL050 is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB).

The PrimeCell KMI can be used to implement a keyboard or mouse interface that is IBM PS2 or AT compatible.

See Keyboard and Mouse Interface, KMI for details of PB-A8 usage and the ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050) Technical Reference Manual (ARM DDI 0143) for full programming details. The physical interface provided by the PB-A8 is shown in Keyboard and mouse interface.

Watchdog Module

The ARM Watchdog Module SP805 is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB).

The Watchdog module consists of a 32-bit down counter with a programmable time-out interval that has the capability to generate an interrupt and a reset signal on timing out. It is intended to be used to apply a reset to a system in the event of a software failure.

See Watchdog for details of PB-A8 usage and the ARM Watchdog Module (SP805) Technical Reference Manual (ARM DDI 0270) for full programming details.

Dual-Timer Module

The Dual-Timer module consists of two programmable 32/16-bit down counters that can generate interrupts on reaching zero.

See Timers for details of PB-A8 usage and the ARM Dual-Timer Module (SP804) Technical Reference Manual (ARM DDI 0271) for full programming details.

General Purpose Input/Output, GPIO

The ARM PrimeCell General Purpose Input/Output (GPIO) PL061 is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB).

The PrimeCell GPIO provides eight programmable inputs or outputs, both software and hardware control modes are supported. An interrupt interface is provided to configure any number of pins as level or transitional interrupt sources.

See General Purpose Input/Output, GPIO for details of PB-A8 usage and the ARM PrimeCell General Purpose Input/Output (PL061) Technical Reference Manual (ARM DDI 0190) for full programming details. The physical interface provided by the PB-A8 is shown in GPIO interface.

Generic Interrupt Controller

The Generic Interrupt controller (GIC) is a custom Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB)

The custom GIC can accept interrupts from multiple sources and generates nFIQ and nIRQ responses for the system.

See Generic Interrupt Controller, GIC for PB-A8 usage, and Interrupts for routing details.

Status and System Control Register Block

The baseboard status and system control registers enable the PB-A8 to determine its environment and to control the on-board systems.

See Status and system control registers for a description of each register.

System Controller

The ARM System Controller SP810 is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB).

The System Controller provides an interface to control the operation of subsystems within the Southbridge. It supports the following functionality:

  • a system mode control state machine

  • crystal and PLL control

  • definition of system response to interrupts

  • reset status capture and soft reset generation

  • Watchdog and Timer module clock enable generation

  • remap control

  • general purpose peripheral control registers

  • system/peripheral clock control and status.

See System Controller (SYSCTRL) for details of PB-A8 usage and the PrimeXsys System Controller (SP810) Technical Reference Manual (ARM DDI 0254) for full programming details.

UART

The ARM PrimeCell UART PL011 is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB).

The PrimeCell UART performs serial-to-parallel conversion of received data and parallel-to-serial conversion of transmitted data. Separate receive and transmit FIFO buffers, a progammable Baud rate generator, hardware or software flow control, and modem support functions are provided.

Note

An IrDA SIR ENDEC interface is implemented by the PrimeCell but this is not supported by the PB-A8.

See UART for details of PB-A8 usage and the ARM PrimeCell UART (PL011) Technical Reference Manual (ARM DDI 0183) for full programming details. The physical interface provided by the PB-A8 is shown in UART interface.

Synchronous Serial Port, SSP

The ARM PrimeCell Synchronous Serial Port (SSP) PL022 is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB).

The PrimeCell SSP is a master or slave interface that enables synchronous serial communication with slave or master peripherals having one of the following:

  • a Motorola SPI-compatible interface

  • a Texas Instruments synchronous serial interface

  • a National Semiconductor Microwire interface.

See Synchronous Serial Port, SSP for details of PB-A8 usage and the ARM PrimeCell Synchronous Serial Port (PL022) Technical Reference Manual (ARM DDI 0194) for full programming details. The physical interface provided by the PB-A8 is shown in Synchronous Serial Port interface.

Smart Card Interface, SCI

The ARM PrimeCell Smart Card Interface (SCI) PL131 is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB).

The PrimeCell Smart Card Interface (SCI) interfaces to an external Smart Card reader. The SCI can autonomously control data transfer to and from the smart card. Transmit and receive data FIFOs are provided to reduce the required interaction between the host system and the peripheral.

See Smart Card Interface, SCI for details of PB-A8 usage and the ARM PrimeCell Smart Card Interface (PL131) Technical Reference Manual (ARM DDI 0228) for full programming details. The physical interface provided by the PB-A8 is shown in Smart Card interface.

Two-wire serial bus interface

The Southbridge implements a custom two-wire serial bus interface that is used to identify the PISMO memory expansion modules present in the PISMO expansion memory socket, and to read and set the time-of-year (TOY) clock on the baseboard. A second interface is used to identify and control display equipment connected to the DVI connector on the rear panel of the ATX enclosure.

Each device on the serial bus has its own slave address. The unique write and read addresses for the PISMO memory and the TOY slave on the serial bus are listed in Table 3.2. The address for the DVI display slave is device dependant and must be obtained from the display manufacturer.

Table 3.2. Serial interface device addresses

DeviceWrite addressRead addressDescription
PISMO (static memory module)0xA20xA3Identifies the type of memory on the board and how it is configured.
TOY (DS1338 RTC)0xD00xD1Reads time data and writes control data to the RTC.
DVI (external display)display dependantdisplay dependantReads the capabilities of the external display connected to the DVI connector on the rear panel of the ATX enclosure. Can control display settings of E-DDC displays.

See Two-wire serial bus interface, SBCon for details of PB-A8 usage and for information on programming the interface.

Real Time Clock, RTC

The ARM PrimeCell Real Time Clock (RTC) PL031 is an Advanced Microcontroller Bus Architecture (AMBA) slave block that connects to the Advanced Peripheral Bus (APB).

The PrimeCell Real Time Clock (RTC) can be used to provide a basic alarm function or long time base counter. An interrupt signal is generated after counting for a programmed number of cycles of real time clock input. Counting in one second intervals is achieved by use of a 1Hz clock input to the PrimeCell RTC.

See Real Time Clock, RTC for details of PB-A8 usage and the ARM PrimeCell Real Time Clock (PL031) Technical Reference Manual (ARM DDI 0224) for full programming details.

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