3.11.1. Setting the Cortex-A8 test chip voltages

The three DACs are updated with voltage control values written to bits [7:0] in the SYS_VOLTAGE_CTLx registers in the Southbridge.

There is a voltage adjustment range of approximately ±10% for the VDDCORE, AVDD, and VDDTC supply voltages. The default value loaded into the SYS_VOLTAGE_CTLx registers at power-on is 0x80. A value of 0xFF gives maximum negative offset from the default, and a value of 0x0 gives maximum positive offset from the default.

See Table 4.26 for details of the registers that set the VDDCORE, AVDD, and VDDTC voltages.


The remaining PB-A8 supply voltages are set during manufacture.

Copyright © 2008-2011 ARM Limited. All rights reserved.ARM DUI 0417D