3.12.1. PB-A8 clocks

This section describes the clocks used by the PB-A8.

ICS307 programmable clock generators

Eight programmable (6-200 MHz) clocks, OSCCLK[7:0] are supplied to the Southbridge by the programmable MicroClock ICS307 clock generators (OSC0-OSC7):

OSCCLK0

Default frequency: 100MHz.

  • generates ACLK for the Northbridge:

    • AXI infrastructure

    • PL340 Dynamic Memory Controller

    • PL081 DMA Controller

    • internal memory

    • peripheral configuration.

  • generates SMCCLK for Northbridge (50MHz).

OSCCLK1

Default frequency: 40MHz. Generates HCLK for the AHB interface between the Southbridge, Northbridge, and Debug FPGA.

OSCCLK2

Default frequency: 25MHz. Generates TSCLK for distribution to the tile site. TSCLK is also supplied to the Northbridge async bridges to synchronize AXI signals to and from the tile site.

OSCCLK3

Default frequency: 50MHz. Generates PCICLK the reference clock for the PCI unit in the Northbridge, and the external PCI and PCI Express bridges.

Note

The PCI external interface speed is determined by the slowest PCI card connected to a PCI expansion slot. The PCI Express external interface speed is 100MHz.

OSCCLK4

Default frequency: 25MHz. Generates CLCDCLK the reference clock for the PL111 CLCD controller in the Northbridge, and the external video DAC and DVI transmitter (1024x768 resolution at 60Hz frame rate support).

OSCCLK5

Default frequency: 50MHz. Generates REFCLK for the Cortex-A8 test chip PLL and Debug FPGA. See PLL for details of the Cortex-A8 PLL.

OSCCLK6

Default frequency: 24MHz. Generates UARTCLK the reference clock for the PL011 UART in the Southbridge.

OSCCLK7

Default frequency: 50MHz. Generates ATCLK (ATB bus clock) and PCLK (debug logic clock) for the Cortex-A8 test chip and Debug FPGA.

The output frequencies of the ICS307s are controlled by divider values loaded into the serial data input pins on the oscillators.

The serial interface logic is implemented in the Southbridge. The only user interface to the clock control logic is through the SYS_OSCx registers. See Oscillator Registers, SYS_OSCx and Oscillator reset registers, SYS_OSCRESETx for programming details.

You can calculate the oscillator output frequency from the formula:

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where:

VDW

Is the VCO divider word (4 - 511) from SYS_OSCx[8:0]

RDW

Is the reference divider word (1 - 127) from SYS_OSCx[15:9]

OD

Is the output divider select (2 to 10) selected from SYS_OSCx[18:16]:

  • b000 selects divide by 10

  • b001 selects divide by 2

  • b010 selects divide by 8

  • b011 selects divide by 4

  • b100 selects divide by 5

  • b101 selects divide by 7

  • b110 selects divide by 3

  • b111 selects divide by 6.

For more information on the ICS clock generator and a frequency calculator, see the IDT web site at www.idt.com.

A crystal on the board provides a fixed frequency 24MHz reference clock for the programmable oscillators OSC0-OSC7 and to generate other fixed frequency clocks in the design.

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