3.14.1. Generic Interrupt Controller

The PB-A8 interrupt controller consists of four custom Generic Interrupt Controllers (GICs).

The GIC allows you to:

The GIC holds three states for each interrupt source:


not asserted


has been asserted, but is not yet complete


processing has started but is not yet complete.

Each GIC contains:


In the PB-A8 there is a single Cortex-A8 processor so only one distributor and one CPU interface is implemented per GIC. In a multiprocessor system, such as the PB11MPCore, a distributor and multiple CPU interfaces are implemented, one CPU interface for each processor.


The Distributor centralizes all interrupt sources and provides the highest priority interrupt to the corresponding CPU interface. Interrupts with a lower priority are forwarded to the appropriate CPU interfaces once they have attained the highest priority.

CPU interface

The CPU interface contains a progammable interrupt priority mask and a binary point mask. It only accepts pending interrupts that have a priority higher than the level set in the priority mask, the binary point mask, and a priority higher than those that the CPU is currently servicing.


The binary point mask is a novel feature of the GIC that allows you to reduce the amount of pre-emption in the system and effectively acts as a pre-emption mask.

Calculating the next interrupt

The algorithm use by the GIC to calculate which interrupt to service next is described by the pseudo code:

if highest pending priority > priority mask
    if no interrupt currently being processed
        issue highest priority pending interrupt
    else if binary point mask calculation > running priority
        pre-empt with highest priority pending interrupt
    end if
end if

A diagram of the algorithm is given in Figure 3.19


The finite state machine shown in Figure 3.19 is repeated for each interrupt source, and for each processor in the system.

See Interrupt signals for the GIC interrupt allocations, and Generic interrupt controller registers for GIC programming details.

Figure 3.19. Interrupt priority calculation

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