4.2.2. Memory characteristics

Table 4.4 lists the DMC and SMC chip selects, and memory range. Addresses not listed are decoded by the Northbridge or the Southbridge for local peripheral selection or are passed to the Logic Tile site.

Table 4.4. Memory chip selects and address range

Chip SelectAddress rangeDevice
DMC CS0

0x70000000-0x7FFFFFFF (0x00000000-0x0FFFFFFF)

DRAM (mirrored)
DMC CS10x80000000-0x8FFFFFFFDRAM
SMC CS00x40000000-0x43FFFFFF (0x00000000-0x00FFFFFF)NOR flash (when remapped: 0x01000000-0x03FFFFFF will be read back as zero)
SMC CS10x44000000-0x47FFFFFFNOR flash
SMC CS20x48000000-0x4BFFFFFFCellular RAM
SMC CS3 Additional address decoding is handled by the CS PLD.0x4C000000-0x4DFFFFFFConfiguration flash
0x4E000000-0x4EFFFFFFEthernet
0x4F000000-0x4FFFFFFFUSB
SMC CS40x50000000-0x53FFFFFF (0x00000000-0x00FFFFFF)

PISMO expansion memory (nCS0) (when remapped: 0x01000000-0x03FFFFFF will be read back as zero)

SMC CS50x54000000-0x57FFFFFFPISMO expansion memory (nCS1)
SMC CS60x58000000-0x5BFFFFFFPISMO expansion memory (nCS2)
SMC CS70x5C000000-0x5FFFFFFFPISMO expansion memory (nCS3)

Copyright © 2008-2011 ARM Limited. All rights reserved.ARM DUI 0417D