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Home > Programmer’s Reference > System Controller (SYSCTRL) > PrimeCell modifications |
The PrimeXsys System Controller (SP810) used in the Southbridge implements only the SYS_CTRL and peripheral ID registers. These registers support the following functionality:
Identification of the build version of the System Controller
Watchdog and timer module clock enable generation
memory remap control.
The function of the bits in the SYS_CTRL0 register at address 0x10001000
is
listed in Table 4.32.
TIMCLK is 1MHz. REFCLK is 32.768kHz.
Table 4.32. SYS_CTRL0 register
Bits | Function |
---|---|
[31:24] | Reserved. Use read-modify-write to preserve value. |
[23] | Watchdog0 enable override. If 0, the enable output is derived from the REFCLK source. If 1, the enable output is forced HIGH. |
[22] | Timer 3 enable override. If 0, the enable output is derived from the Timing Reference Select signal. If 1, the enable output is forced HIGH. |
[21] | Timer 3 enable/ Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK. |
[20] | Timer 2 enable override. If 0, the enable output is derived from the Timing Reference Select signal. If 1, the enable output is forced HIGH. |
[19] | Timer 2 enable/ Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK. |
[18] | Timer 1 enable override. If 0, the enable output is derived from the Timing Reference Select signal. If 1, the enable output is forced HIGH. |
[17] | Timer 1 enable/ Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK. |
[16] | Timer 0 enable override. If 0, the enable output is derived from the Timing Reference Select signal. If 1, the enable output is forced HIGH. |
[15] | Timer 0 enable/ Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK. |
[14:10] | Reserved. Use read-modify-write to preserve value. |
[9] | Remap status. This read-only bit returns the remap status. |
[8] | Remap clear request. Set this bit to disable
memory remapping and return to normal mapping with dynamic memory
selected for memory accesses to the region 0x00000000-0x00FFFFFF . |
[7:0] | Reserved. Use read-modify-write to preserve value. |
The function of the bits in the SYS_CTRL1 register at address 0x1001A000
is
listed in Table 4.33.
Table 4.33. SYS_CTRL1 register
Bits | Function |
---|---|
[31:24] | Reserved. Use read-modify-write to preserve value. |
[23] | Watchdog1 enable override. If 0, the enable output is derived from the REFCLK source. If 1, the enable output is forced HIGH. |
[22] | Timer7 enable override. If 0, the enable output is derived from the Timing Reference Select signal. If 1, the enable output is forced HIGH. |
[21] | Timer7 enable/ Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK. |
[20] | Timer6 enable override. If 0, the enable output is derived from the Timing Reference Select signal. If 1, the enable output is forced HIGH. |
[19] | Timer6 enable/ Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK. |
[18] | Timer5 enable override. If 0, the enable output is derived from the Timing Reference Select signal. If 1, the enable output is forced HIGH. |
[17] | Timer5 enable/ Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK. |
[16] | Timer4 enable override. If 0, the enable output is derived from the Timing Reference Select signal. If 1, the enable output is forced HIGH. |
[15] | Timer4 enable/ Timer Reference Select. If 0, the timing reference is REFCLK. If 1, the timing reference is TIMCLK. |
[14:10] | Reserved. Use read-modify-write to preserve value. |
[9] | Reserved. Use read-modify-write to preserve value. |
[8] | Reserved. Use read-modify-write to preserve value. |
[7:0] | Reserved. Use read-modify-write to preserve value. |