4.6.1. Display resolutions and display memory organization

Use registers CLCD_TIM0, CLCD_TIM1, CLCD_TIM2, and SYS_OSCCLK4 to define the display timings. Table 4.37 lists the register and clock values for different display resolutions.

Table 4.37. Values for different display resolutions

Display resolutionCLCDCLK frequency and SYS_OSCCLK4 register value CLCD_TIM0 register at 0x10020000CLCD_TIM1 register at 0x10020004CLCD_TIM2 register at 0x10020008
QVGA(240x320) (portrait) on VGA25MHz, 0x2C770xC7A7BF380x595B613F0x04eF1800
QVGA (320x240) (landscape) on VGA25MHz, 0x2C770x9F7FBF4C0x818360eF0x053F1800
QCIF (176x220) (portrait) on VGA25MHz, 0x2C770xe7C7BF280x8B8D60DB0x04AF1800
VGA (640x480) on VGA25MHz, 0x2C770x3F1F3F9C0x090B61DF0x067F1800
SVGA (800x600) on SVGA36MHz, 0x2CAC0x1313A4C40x0505F6570x071F1800
Epson 2.2in panel QCIF (176x220)16MHz, 0x2C480x020102280x010004DB0x04AF3800
Sanyo 3.8in panel QVGA (320x240)10MHz, 0x2C2A0x0505054C0x050514eF0x053F1800

The mapping of the 32 bits of pixel data in memory to the RGB display signals depends on the resolution and display mode.

For details on setting the red, green, and blue brightness for direct (non-palettized) 24-bit and 16-bit color modes see the CLCD Technical Reference Manual. Selftest example code, that displays 24-bit and 16-bit VGA images, is provided on the accompanying CD.

Note

For resolutions based on one to sixteen bits per pixel, multiple pixels are encoded into each 32-bit word.

All monochrome modes, and color modes using 8 or fewer bits per pixel, use the palette to encode the color value from the data bits, see the CLCD Technical Reference Manual for details.

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