RealView® Platform Baseboard for Cortex™-A8 User Guide

HBI-0178 HBI-0176 HBI-0175


Table of Contents

Preface
About this book
Intended audience
Using this book
Product revision status
Typographical conventions
Other conventions
Further reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. Precautions
1.1.1. Ensuring safety
1.1.2. Preventing damage
1.2. About the PB-A8
1.2.1. Cortex-A8 test chip
1.2.2. Debug FPGA
1.2.3. Northbridge
1.2.4. Southbridge
1.2.5. PB-A8 expansion
2. Getting Started
2.1. Setting up the baseboard
2.2. Boot Monitor configuration
2.3. JTAG debugger and USB config support
2.3.1. JTAG debugger
2.3.2. USB config port
2.4. Baseboard configuration switches
2.4.1. Boot memory configuration
2.4.2. Tile site clock frequency
3. Hardware Description
3.1. PB-A8 architecture
3.1.1. Bypassing the power switch
3.1.2. Top level architecture
3.1.3. Cortex-A8 test chip
3.1.4. Debug FPGA
3.1.5. Northbridge
3.1.6. Southbridge
3.1.7. PCI bus connectors
3.1.8. Displays
3.1.9. Logic Tile expansion
3.1.10. Clock generation
3.1.11. Debug, Trace and USB Config support
3.2. Tile interconnections
3.2.1. AXI bus multiplexing
3.3. Cortex-A8 test chip
3.3.1. Cortex-A8 test chip overview
3.4. Debug FPGA
3.5. Northbridge
3.5.1. Cortex-A8 test chip interface
3.5.2. CLCD controller
3.5.3. Memory controllers
3.5.4. Multiplexed AHB-Lite interface
3.5.5. Multiplexed AXI interfaces
3.5.6. PCI interface
3.6. Southbridge
3.6.1. FPGA configuration
3.6.2. Reset controller
3.6.3. CompactFlash
3.6.4. APB peripherals
3.7. Ethernet interface
3.8. USB Interface
3.9. DVI Interface
3.10. PCI interface
3.11. Power supply control
3.11.1. Setting the Cortex-A8 test chip voltages
3.11.2. Reading the Cortex-A8 test chip voltages
3.11.3. Reading the Cortex-A8 test chip currents
3.12. Clock architecture
3.12.1. PB-A8 clocks
3.12.2. PLL
3.12.3. Northbridge clocks
3.12.4. Southbridge clocks
3.13. Resets
3.14. Interrupts
3.14.1. Generic Interrupt Controller
3.15. Test, configuration, debug and trace interfaces
3.15.1. Debug and Config port support
3.15.2. USB config interface
3.15.3. Integrated logic analyzer (ILA)
4. Programmer’s Reference
4.1. Memory map
4.2. Configuration and initialization
4.2.1. Remapping of boot memory
4.2.2. Memory characteristics
4.3. Status and system control registers
4.3.1. ID Register, SYS_ID
4.3.2. User Switch Register, SYS_USERSW
4.3.3. LED Register, SYS_LED
4.3.4. Oscillator Registers, SYS_OSCx
4.3.5. Lock Register, SYS_LOCK
4.3.6. 100Hz Counter, SYS_100HZ
4.3.7. Flag Registers, SYS_FLAGSx and SYS_NVFLAGSx
4.3.8. Reset Control Register, SYS_RESETCTL
4.3.9. MCI Register, SYS_MCI
4.3.10. Flash Control Register, SYS_FLASH
4.3.11. CLCD Control Register, SYS_CLCD
4.3.12. Configuration select switch, SYS_CFGSW
4.3.13. 24MHz Counter, SYS_24MHZ
4.3.14. Miscellaneous flags, SYS_MISC
4.3.15. DMA peripheral map register, SYS_DMAPSR
4.3.16. PCI Express status register, SYS_PEX_STAT
4.3.17. PCI status register, SYS_PCI_STAT
4.3.18. PLD control register 1, SYS_PLD_CTRL1
4.3.19. PLD control register 2, SYS_PLD_CTRL2
4.3.20. PLL initialization register, SYS_PLL_INIT
4.3.21. Processor ID register 0, SYS_PROCID0
4.3.22. Processor ID register 1, SYS_PROCID1
4.3.23. Oscillator reset registers, SYS_OSCRESETx
4.3.24. Voltage control registers, SYS_VOLTAGE_CTLx
4.3.25. Oscillator test registers, SYS_TEST_OSCx
4.3.26. Debug control and status register, SYS_DEBUG
4.3.27. Test mode register, SYS_TESTMODE
4.3.28. PLL Reset register, SYS_PLL_RESET
4.4. System Controller (SYSCTRL)
4.4.1. PrimeCell modifications
4.5. Advanced Audio CODEC Interface, AACI
4.5.1. PrimeCell Modifications
4.6. Color LCD Controller, CLCDC
4.6.1. Display resolutions and display memory organization
4.7. Single Master Direct Memory Access Controller, SMDMAC
4.7.1. DMAC flow control
4.7.2. DMA channel allocation
4.8. Dynamic Memory Controller, DMC
4.8.1. Register values
4.9. Ethernet
4.10. General Purpose Input/Output, GPIO
4.10.1. Onboard I/O control
4.11. Generic Interrupt Controller, GIC
4.11.1. Interrupt signals
4.11.2. Generic interrupt controller registers
4.11.3. Handling interrupts
4.12. Keyboard and Mouse Interface, KMI
4.13. MultiMedia Card Interface, MCI
4.14. AXI to PCI bridge
4.14.1. Addresses
4.14.2. Interrupts
4.15. Real Time Clock, RTC
4.16. Two-wire serial bus interface, SBCon
4.17. Smart Card Interface, SCI
4.18. Synchronous Serial Port, SSP
4.19. Static Memory Controller, SMC
4.20. Timers
4.21. UART
4.21.1. PrimeCell Modifications
4.22. USB interface
4.23. Watchdog
4.24. CompactFlash interface
4.24.1. CompactFlash Control Register, CF_CTRL
A. Signal Descriptions
A.1. Compact Flash interface
A.2. Audio CODEC interface
A.3. MMC and SD card interface
A.4. Keyboard and mouse interface
A.5. GPIO interface
A.6. UART interface
A.7. Synchronous Serial Port interface
A.8. Smart Card interface
A.9. Ethernet interface
A.10. USB interface
A.11. DVI display interface
A.12. RealView Logic Tile header connectors
A.12.1. HDRX signals
A.12.2. HDRY signals
A.12.3. HDRZ signals
A.13. Test and debug connections
A.13.1. JTAG
A.13.2. USB config port
A.13.3. Integrated Logic Analyzer (ILA)
A.13.4. Trace Connectors
B. Specifications
B.1. Electrical Specification
B.1.1. Bus interface characteristics
B.2. Timing specifications
B.2.1. Clock frequency restrictions
B.2.2. AXI bus timings
C. Memory Expansion Boards
C.1. About memory expansion
C.1.1. Operation without expansion memory
C.1.2. Memory board configuration
C.2. Fitting a memory board
C.3. Connector pinout
C.3.1. Expansion connector
D. RealView Logic Tile Expansion
D.1. About the RealView Logic Tile
D.2. Header connectors
D.2.1. Variable I/O levels
D.2.2. RealView Logic Tile clock
D.2.3. JTAG
D.2.4. AXI buses used by the Northbridge and RealView Logic Tiles
D.2.5. Reset
E. Boot Monitor and platform library
E.1. About the Boot Monitor
E.2. About the platform library
E.3. Using the baseboard Boot Monitor and platform library
E.3.1. Boot Monitor configuration switches
E.3.2. Running the Boot Monitor
E.3.3. Loading Boot Monitor into NOR flash
E.3.4. Redirecting character output to hardware devices
E.3.5. Using a boot script to run an image automatically
E.3.6. Rebuilding the Boot Monitor or platform library
E.3.7. Building an application with the platform library
E.3.8. Building an application that uses semihosting
E.3.9. Loading and running an application from NOR flash
E.3.10. Running an image from MMC or SD card or CompactFlash
E.3.11. Using the Network Flash Utility
F. Boot Monitor Commands
F.1. About Boot Monitor commands
F.2. Boot Monitor command set
G. Loading FPGA Images
G.1. General procedure
G.2. Board files
G.2.1. Naming conventions for board files
G.2.2. Naming conventions for image files
G.3. The progcards utilities
G.4. Upgrading your hardware
G.4.1. Procedure for progcards_rvi.exe
G.4.2. Procedure for progcards_usb.exe
G.4.3. Troubleshooting
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Cortex-A8 system architecture
3.1. Baseboard layout
3.2. Front panel layout
3.3. Rear panel layout
3.4. PB-A8 top level architecture diagram
3.5. Tile site and main system bus routing
3.6. top-level view of Cortex-A8 test chip
3.7. top level view of the Debug FPGA
3.8. Northbridge block diagram
3.9. Southbridge block diagram
3.10. PCI-PCI Express interface
3.11. PB-A8 OSCx clock routing
3.12. Test chip PLL and output divider
3.13. PLL clock frequency equations
3.14. Northbridge clock domains
3.15. Reset domains
3.16. Reset Controller state diagram
3.17. Reset timings
3.18. Internal and tile site interrupt routing
3.19. Interrupt priority calculation
4.1. System memory map
4.2. SYS_ID register
4.3. SYS_USERSW register
4.4. SYS_LED register
4.5. SYS_OSCx register
4.6. SYS_LOCK register
4.7. 100Hz Counter, SYS_100HZ register
4.8. SYS_RESETCTL register
4.9. SYS_MCI register
4.10. SYS_FLASH register
4.11. SYS_CLCD register
4.12. SYS_CFGSW register
4.13. SYS_24MHZ register
4.14. SYS_MISC register
4.15. SYS_DMAPSR register
4.16. SYS_PEX_STAT register
4.17. SYS_PCI_STAT register
4.18. SYS_PLD_CTRL1 register
4.19. SYS_PLD_CTRL2 register
4.20. SYS_PLL_INIT register
4.21. SYS_PROCID0 register
4.22. SYS_PROCID1 register
4.23. SYS_OSCRESETx register
4.24. SYS_DEBUG register
4.25. SYS_TESTMODE register
4.26. SYS_PLL_RESET register
4.27. AACI ID register
4.28. CPU control register
4.29. Priority mask register
4.30. Binary point register
4.31. Binary point example
4.32. Interrupt acknowledge register
4.33. End of interrupt register
4.34. Running interrupt register
4.35. Highest pending interrupt register
4.36. Distributor control register
4.37. Controller type register
4.38. Set-enable1 register
4.39. Set-enable2
4.40. Clear-enable1 register
4.41. Clear-enable2 register
4.42. Set-pending1 register
4.43. Set-pending2 register
4.44. Clear-pending1 register
4.45. Clear-pending2 register
4.46. Active1 register
4.47. Active2 register
4.48. Priority register
4.49. CPU targets register
4.50. Configuration register
4.51. Software interrupt register
4.52. CF_CTRL Register
A.1. Compact Flash connector pin numbering
A.2. Audio connectors
A.3. MMC/SD card socket pin numbering
A.4. MMC card
A.5. KMI connector
A.6. GPIO connector
A.7. Serial interface connector
A.8. SSP expansion interface
A.9. Smartcard contacts assignment
A.10. SCI expansion
A.11. Ethernet connector
A.12. USB connectors
A.13. DVI connector
A.14. HDRX, HDRY, and HDRZ pin numbering
A.15. JTAG connector
A.16. USB debug connector
A.17. Integrated Logic Analyzer (ILA) connector
A.18. AMP Mictor connector
B.1. Tile site multiplexed AXI timing
C.1. Static memory board block diagram
C.2. Samtec 120-way connector
D.1. Signal groups on the PB-A8 tile site
D.2. HDRX, HDRY, and HDRZ (upper) pin numbering

List of Tables

2.1. Boot Monitor startup behavior
2.2. STDIO redirection
2.3. Selecting the boot device
2.4. Tile site frequency options
3.1. FPGA image selection
3.2. Serial interface device addresses
3.3. VCO specification
4.1. System memory map
4.2. Memory map for standard peripherals
4.3. Boot memory
4.4. Memory chip selects and address range
4.5. Register map for status and system control registers
4.6. SYS_ID register bit assignments
4.7. SYS_OSCx registers
4.8. SYS_OSCx register bit assignments
4.9. SYS_LOCK register bit assignments
4.10. Flag registers
4.11. SYS_RESETCTL register bit assignments
4.12. SYS_MCI register bit assignment
4.13. SYS_FLASH register bit assignments
4.14. SYS_CLCD register bit register assignments
4.15. SYS_MISC register bit assignment
4.16. SYS_DMAPSR register bit assignments
4.17. SYS_DMAPSR register bit coding
4.18. SYS_PEX_STAT register bit assignments
4.19. SYS_PCI_STAT register bit assignments
4.20. SYS_PLD_CTRL1 register bit assignments
4.21. SYS_PLD_CTRL2 register bit assignments
4.22. SYS_PLL_INIT register bit assignments
4.23. SYS_PROCID0 register bit assignments
4.24. SYS_PROCID1 register bit assignments
4.25. SYS_OSCRESETx registers
4.26. SYS_VOLTAGE_CTLx registers
4.27. SYS_TEST_OSCx registers
4.28. SYS_DEBUG register
4.29. SYS_TESTMODE register
4.30. SYS_PLL_RESET register
4.31. SYSCTRL implementation
4.32. SYS_CTRL0 register
4.33. SYS_CTRL1 register
4.34. AACI implementation
4.35. Modified AACI PeriphID3 register
4.36. CLCDC implementation
4.37. Values for different display resolutions
4.38. SMDMAC implementation
4.39. DMC implementation
4.40. Ethernet implementation
4.41. GPIO implementation
4.42. GPIO2 and MCI status signals
4.43. Generic Interrupt Controller implementation
4.44. GIC interrupt allocation
4.45. Interrupt control register addresses
4.46. CPU interface registers address offset values
4.47. CPU control register
4.48. Priority mask
4.49. Binary point
4.50. Binary Point bit values assignment
4.51. Interrupt acknowledge
4.52. End of interrupt
4.53. Running interrupt
4.54. Highest pending interrupt
4.55. Distribution registers address offset values
4.56. Distributor control
4.57. Controller type
4.58. Set-enable1
4.59. Reserved interrupts
4.60. Set-enable2
4.61. Reserved interrupts
4.62. Clear-enable1
4.63. Clear-enable2
4.64. Set-pending1
4.65. Set-pending2
4.66. Clear-pending1
4.67. Clear-pending2
4.68. Active1
4.69. Active2
4.70. Priority register address offsets and Interrupt IDs
4.71. CPU targets register address offsets and Interrupt IDs
4.72. Configuration register address offsets
4.73. Software interrupt
4.74. KMI implementation
4.75. MCI implementation
4.76. AXI to PCI bridge implementation
4.77. PCI bus memory map
4.78. PCI slot interrupt mappings
4.79. PCI virtual interrupt mappings
4.80. RTC implementation
4.81. Serial bus implementation
4.82. Serial interface device addresses
4.83. SBCon 0 serial bus register
4.84. SBCon 1 serial bus register
4.85. SCI implementation
4.86. SSP implementation
4.87. SMC implementation
4.88. Timer implementation
4.89. UART implementation
4.90. USB implementation
4.91. USB controller base address
4.92. Watchdog implementation
4.93. CompactFlash implementation
4.94. CF_CTRL register bit assignments
A.1. Compact Flash connector pinout
A.2. Multimedia Card interface signals
A.3. Mouse and keyboard port signal descriptions
A.4. Serial interface signal assignment
A.5. SSP signal assignment
A.6. Smartcard connector signal assignment
A.7. Signals on SCI expansion connector
A.8. Ethernet signals
A.9. DVI connector signals
A.10. HDRX signals
A.11. HDRY signals
A.12. HDRZ signals
A.13. Trace Port A (TRACEA) connector J54
A.14. Trace Port B (TRACEB) connector J55
B.1. Baseboard electrical characteristics
B.2. AC Specifications
C.1. Static memory connector signals
E.1. STDIO redirection
E.2. platform library options
E.3. NFU commands
E.4. NFU MANAGE commands
F.1. Standard Boot Monitor command set
F.2. MMC, SD, and CompactFlash card sub-menu commands
F.3. Boot Monitor Configure commands
F.4. Boot Monitor Debug commands
F.5. Boot Monitor NOR flash commands

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

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The system should be powered down when not in use.

The PB-A8 generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • ensure attached cables do not lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment and the receiver

  • connect the equipment into an outlet on a circuit different from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technician for help

Note

It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision AMay 2008First release
Revision BMarch 2009Fixed reported defects and added requested enhancements
Revision CJuly 2010Document update
Revision DApril 2011Document update
Copyright © 2008-2011 ARM Limited. All rights reserved.ARM DUI 0417D