Rating: 2.

In general, the functional effect of any operation in the system control co-processor, CP15 is not guaranteed to occur until after an Instruction Synchronization Barrier (ISB) is subsequently executed, or an exception entry or return occurs. There are several exceptions to this rule. Some guarantee earlier visibility in certain circumstances, and others require extra steps to guarantee that the operation takes place. These are described more fully in the ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition.

When parameter delayed_CP15_operations is set to true, the functional effects of the CP15 operations are postponed for as long as the model determines that it is legal to do so. That is, until the specified barrier is executed, or other ordering requirements force earlier completion.

Table A.1 shows the barrier type to be executed for the functional effect of specific cache and branch prediction operations to be seen in the model.

All other CP15 operations not listed in Table A.1 are postponed until an Instruction Synchronization Barrier (ISB) is executed or an exception entry or return occurs, subject to ordering requirements.

Where a Data Memory Barrier (DMB) is specified as the required barrier, a Data Synchronization Barrier (DSB) is a suitable alternative.

For more information on barrier requirements, see the sections relating to TLB maintenance, ordering of cache and branch predictor maintenance operations, and changes to CP15 registers and the memory order model in the ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition.