Rating: 1.

The architecture specifies that behavior can be unpredictable when the same physical memory location has any of the following contradictory combinations of memory marking:

Such memory marking contradictions can occur, for example:

When parameter vmsa.memory_marking_check is set true, the model emits a warning when the TLB of a core, or of any two cores inside the inner shared domain, are loaded with multiple entries for one physical address that fail to obey the restrictions listed.

You can use this feature most effectively with the aggressively pre-fetching TLB. See Aggressively pre-fetching TLB.