Rating: 3.

The ARMv7 architecture employs what is called a weakly-ordered memory model. This means that, with certain limits, the order of load and store operations performed by the core is not expected to be the same as the program order.

The model can reorder memory read operations (from LDR, LDM and LDD instructions) with respect to each other, store operations, and certain other instructions. To enable this functionality, set the parameter vmsa.delayed_read_buffer=1 for the processor, and also set cpu[n].use_IR=3 for each core that is to participate in reordering.

When stepping through programs in Model Debugger, a reordered load is evident when the destination register of a load instruction is displayed as 0xAFAFAFAF (or 0xAFAF or 0xAF for sub-word operations). The real value is loaded into the destination register when that value is required for an operation that cannot be deferred any further, for example when it is used to compute the address of a subsequent memory access.

If the value is never needed, for example when another value is written into the destination register before it is ever read, then the deferred operation is killed instead. In such cases, it is likely that the load operation is not visible from outside the core, and it also does not cause its usual side-effects such as filling cache lines.