The PL030_RTC component is a programmer's view model of the PL030_RTC PrimeCell. For a detailed description of the behavior of the PrimeCell, read the technical reference manual. See the ARM PrimeCell Real Time Clock (PL030) Technical Reference Manual.
Figure 5.25 shows a view of the component in System Canvas.
This component is written in LISA+.
Table 5.37 provides a brief description of the ports. See the PL030 documentation for more details.
Table 5.37. PL030_RTC ports
| Name | Port protocol | Type | Description |
|---|---|---|---|
| pvbus | PVBus | Slave | Slave port for connection to PV bus master/decoder. |
| intr | Signal | Master | Interrupt signaling. |
| clock | ClockSignal | Slave | Clock input, typically 1MHz, driving master count rate. |
Table 5.38 provides a description of the configuration registers for the PL030_RTC component. See the PL030 documentation for further details.
Table 5.38. PL030_RTC registers
| Register name | Offset | Access | Description |
|---|---|---|---|
| RTCDR | 0x00 | read only | Data register. |
| RTCMR | 0x04 | read/write | Match register. |
| RTCSTAT | 0x08 | read only | Interrupt status register. |
| RTCEOI | 0x08 | write only | Interrupt clear register. |
| RTCLR | 0x0C | read/write | Counter load register. |
| RTCCR | 0x10 | read/write | Counter register. |
The PL030_RTC component has been tested as part of the VE example system using VE test suites and by booting operating systems.
The PL030_RTC component has no impact on the performance of a PV system when idle or counting down. The component only executes code when the counter expires or during bus accesses.
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