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| Non-Confidential | ID051811 |
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Fast Models implement two different types of cache model:
Register model.
Functional model.
A register model provides all the cache control registers so that cache operations succeed, but does not model the state of the cache. All accesses go to memory.
A functional model tracks cache state and its contents at each level of the memory hierarchy. If cache management is not done correctly, incorrect data might be returned, as it would on real hardware.
Fast Models provide:
Register models of caches on all processors that support caches and also the PL310 cache controller.
Functional models of L1 caches on Cortex-A5, Cortex-A8, Cortex-A9 and Cortex-R4 processors, the L2 cache on the Cortex-A8, and the PL310 cache controller.
| Copyright © 2008-2011 ARM. All rights reserved. | ARM DUI 0423J |
| Non-Confidential | ID051811 |
| PDF version | |
| Home > Accuracy and Functionality > Functional caches in Fast Models |