Caches and write buffers are not modeled, so all memory access timing is effectively zero wait state.

All instructions execute, in aggregate, in one cycle of the component master clock input.

Interrupts are not taken at every instruction boundary.

Some sequences of instructions are executed atomically, ahead of the master clock of a component, so that system time does not advance during execution. This can sometimes have an effect in sequential access of device registers where devices are expecting time to move on between each access.

DMA to and from Tightly Coupled Memory (TCM) is currently atomic.