Fast Models Reference Manual: 4.4.3. Parameters

Fast Models Reference Manual

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4.4.3. Parameters

Table 4.8 lists the parameters set at the processor level for the ARMCortexA9UPCT component.

Table 4.8. ARMCortexA9UPCT parameters^[4]

Parameter	Description	Type	Allowed value	Default value
`CLUSTER_ID`	CPU cluster ID value.	integer	0-15	0
`device-accurate-tlb`	Specify whether all TLBs are modeled.	boolean	true/false	false^[a]
`dcache-state_modelled`	Set whether D-cache has stateful implementation.	boolean	true/false	false
`icache-state_modelled`	Set whether I-cache has stateful implementation.	boolean	true/false	false
^[4]For the ARMCortexA9UP processor, the instance name for the processor consists of the normal instance name (in the provided examples, cortile.core) with a suffix of cpu0. In the example Cortex-A9 platform the instance name is cortile.core.cpu0 ^[a]Specifying `false` models enables modeling a different number of TLBs if this improves simulation performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Specify `true` if device accuracy is required.

Table 4.9 provides a description of the CPU configuration parameters for the ARMCortexA9UPCT component.

Table 4.9. ARMCortexA9UPCT individual processor parameters

Parameter	Description	Type	Allowed value	Default value
`CFGEND`	Initialize to BE8 endianness.	boolean	true/false	false
`CFGNMFI`	Enable non-maskable fast interrupts on startup.	boolean	true/false	false
`CP15SDISABLE`	Initialize to disable access to some CP15 registers.	boolean	true/false	false
`TEINIT`	Thumb exception enable. The default has exceptions including reset handled in ARM state.	boolean	true/false	false
`VINITHI`	Initialize with high vectors enabled.	boolean	true/false	false
`POWERCTLI`	Default power control state for CPU.	integer	0-3	0
`ase-present`^[a]	Set whether model has NEON support.	boolean	true/false	true
`semihosting-cmd_line`^[b]	Command line available to semihosting SVC calls.	string	no limit except memory	[empty string]
`semihosting-debug`^[c]	Enable debug output of semihosting SVC calls.	boolean	true/false	false
`semihosting-enable`	Enable semihosting SVC traps. Caution Applications that do not use semihosting must set this parameter to false.	boolean	true/false	true
`semihosting-ARM_SVC`	ARM SVC number for semihosting.	integer	`0x000000 - 0xFFFFFF`	`0x123456`
`semihosting-Thumb_SVC`	Thumb SVC number for semihosting.	integer	`0x00 - 0xFF`	`0xAB`
`semihosting-heap_base`	Virtual address of heap base.	integer	`0x00000000 - 0xFFFFFFFF`	`0x0`
`semihosting-heap_limit`	Virtual address of top of heap.	integer	`0x00000000 - 0xFFFFFFFF`	`0x0F000000`
`semihosting-stack_base`	Virtual address of base of descending stack.	integer	`0x00000000 - 0xFFFFFFFF`	`0x10000000`
`semihosting-stack_limit`	Virtual address of stack limit.	integer	`0x00000000 - 0xFFFFFFFF`	`0x0F000000`
`vfp-enable_at_reset`^[d]	Enable coprocessor access and VFP at reset.	boolean	true/false	false
`vfp-present`^[a]	Set whether the model has VFP support.	boolean	true/false	true
`dcache-size`	Set D-cache size in bytes.	integer	16KB, 32KB, or 64KB	`0x8000`
`icache-size`	Set I-cache size in bytes.	integer	16KB, 32KB, or 64KB	`0x8000`
^[a]The ase-present and vfp-present parameters configure the synthesis options for the Cortex-A9 model. The options are: vfp present and ase present NEON and VFPv3-D32 supported. vfp present and ase not present VFPv3-D16 supported. vfp not present and ase present Illegal. Forces vfp-present to true so model has NEON and VFPv3-D32 support. vfp not present and ase not present Model has neither NEON nor VFPv3-D32 support. ^[b]The value of argv[0] points to the first command line argument, not to the name of an image. ^[c]Currently ignored. ^[d]This is a model specific behavior with no hardware equivalent.

Note

For the ARMCortexA9UP processor, the instance name for the processor consists of the normal instance name (in the provided examples, cortile.core) with a suffix of cpu0. In the example Cortex-A9 platform the instance name is cortile.core.cpu0.

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