Fast Models Reference Manual: 4.9.1. Ports

4.9.1. Ports

Table 4.21 provides a brief description of the ports in the ARMCortexR4CT component. Refer to the processor technical reference manual for more details.

Table 4.21. ARMCortexR4CT ports

Name	Port protocol	Type	Description
`clk_in`	ClockSignal	slave	clock input
`pvbus_m`	PVBus	master	master port for all memory accesses
`reset`	Signal	slave	asynchronous reset signal input
`irq`	Signal	slave	asynchronous IRQ signal input
`fiq`	Signal	slave	asynchronous FIQ signal input
`pmuirq`	Signal	master	performance monitoring unit IRQ output
`vic_addr`	ValueState	slave	address input for connection to PL192 VIC
`vic_ack`	Signal	master	acknowledge signal output for PL192 VIC
`cfgie`^[a]	Signal	slave	configure instruction endianness after a reset
`ticks`	InstructionCount	master	output that can be connected to a visualization component
`cfgend0`	Signal	slave	initialize to BE8 endianness after a reset
`cfgnmfi`	Signal	slave	enable non-maskable fast interrupts after a reset
`cfgte`	Signal	slave	initialize to take exceptions in Thumb state after a reset
`vinithi`	Signal	slave	initialize with high vectors enabled after a reset
`standbywfi`	Signal	master	signal that the processor is in standby waiting for interrupts
`initrami`	Signal	slave	initialize with ITCM enabled after reset
`initramd`	Signal	slave	initialize with DTCM enabled after reset
`itcm`	PVBus	slave	slave access to ITCM
`dtcm`	PVBus	slave	slave access to DTCM
^[a]This is implemented in the model, although it is optional in hardware.

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