Fast Models Reference Manual: 4.10.1. Ports

4.10.1. Ports

Table 4.23 provides a brief description of the ports in the ARMCortexM4CT component. Refer to the processor technical reference manual for more details.

Table 4.23. ARMCortexM4CT ports

Name	Port protocol	Type	Description
`auxfault`	Value	slave	auxiliary fault status information
`bigend`	Signal	slave	configure endianness after a reset
`clk_in`	ClockSignal	slave	clock input
`currpri`	Value	master	indicates the current execution priority of the processor
`edbgrq`	Signal	master	external debug request
`event`	Signal	peer	event input and output for wakeup from WFE. This port combines the TXEV and RXEVsignals
`intisr[0-239]`	Signal	slave	external interrupt signals
`intnmi`	Signal	slave	non-maskable interrupt
`lockup`	Signal	master	asserted when processor is in lockup state
`poreset`	Signal	slave	asynchronous power-on reset signal input
`pvbus_m`	PVBus	master	master port for all memory accesses except those on the External Private Peripheral Bus
`pv_ppbus_m`	PVBus	master	master port for memory accesses on the External Private Peripheral Bus
`reset`	Signal	slave	asynchronous reset signal input (not debug components)
`sleepdeep`	Signal	master	indicates that the processor is in deep sleep
`sleeping`	Signal	master	indicates that the processor is in sleep
`stcalib`	Value	slave	SysTick calibration value
`stclk`	ClockSignal	slave	reference clock input for SysTick
`sysreset`	Signal	slave	asynchronous reset signal input
`sysresetreq`	Signal	master	system reset request
`ticks`	InstructionCount	master	output that can be connected to a visualization component
`dbgen`^[a]	Signal	slave	enable hardware debugger access
`fpudisable`	Signal	slave	disable FPU on next reset
`mpudisable`	Signal	slave	disable MPU on next reset
`fpxxc`	Value	master	cumulative exception flags from the Floating Point Status and Control Register (FPSCR). This value port combines the five RTL signals FPIXC, FPIDC, FPOFC, FPUFC, FPDZC and FPIOC.
^[a]Since the CT model does not provide a DAP port or halting debug capability, this signal is ignored.

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