Fast Models Reference ManualVersion 7.1
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Fast Models Reference Manual

Version 7.1

Copyright © 2008-2012 ARM. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this book
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the components
2. Accuracy and Functionality
2.1. Model Capabilities Overview
2.1.1. What Fast Models can do
2.1.2. What Fast Models cannot do
2.2. Functional caches in Fast Models
2.2.1. Configuring functional caches
2.2.2. Performance effects of enabling functional caches
2.3. How Accurate are Fast Models?
2.3.1. Timing
2.3.2. Bus traffic
2.3.3. Instruction prefetch
2.3.4. Out-of-order execution and write-buffers
2.3.5. Caches
3. Framework Protocols
3.1. About the framework and protocols
3.1.1. Signaling protocols
3.1.2. Clocking components and protocols
3.1.3. Debug interface protocols
3.2. Signaling Protocols
3.2.1. Signal protocol
3.2.2. StateSignal protocol
3.2.3. Value protocol
3.2.4. ValueState protocol
3.3. Clocking components and protocols
3.3.1. MasterClock component
3.3.2. ClockDivider component
3.3.3. ClockTimer component
3.3.4. ClockTimer64 component
3.4. Debug interface protocols
3.4.1. CADIProtocol
3.4.2. CADIDisassemblerProtocol
4. Processor Components
4.1. About the Code Translation processor components
4.2. ARMCortexA15xnCT
4.2.1. Ports
4.2.2. Additional protocols
4.2.3. Parameters
4.2.4. Registers
4.2.5. Caches
4.2.6. Debug Features
4.2.7. Verification and Testing
4.2.8. Performance
4.2.9. Library dependencies
4.2.10. Differences between the CT model and RTL Implementations
4.3. ARMCortexA9MPxnCT
4.3.1. Ports
4.3.2. Additional protocols
4.3.3. Parameters
4.3.4. Registers
4.3.5. Caches
4.3.6. Debug features
4.3.7. Verification and testing
4.3.8. Performance
4.3.9. Library dependencies
4.3.10. Differences between the CT model and RTL implementations
4.4. ARMCortexA9CT
4.4.1. Ports
4.4.2. Additional protocols
4.4.3. Parameters
4.4.4. Registers
4.4.5. Caches
4.4.6. Debug features
4.4.7. Verification and testing
4.4.8. Performance
4.4.9. Library dependencies
4.4.10. Differences between the CT model and RTL implementations
4.5. ARMCortexA8CT
4.5.1. Ports
4.5.2. Additional protocols
4.5.3. Parameters
4.5.4. Registers
4.5.5. Caches
4.5.6. Debug features
4.5.7. Verification and testing
4.5.8. Performance
4.5.9. Library dependencies
4.5.10. Differences between the CT model and RTL implementations
4.6. ARMCortexA7xnCT
4.6.1. Ports
4.6.2. Additional protocols
4.6.3. Parameters
4.6.4. Registers
4.6.5. Caches
4.6.6. Debug Features
4.6.7. Verification and Testing
4.6.8. Performance
4.6.9. Library dependencies
4.6.10. Differences between the CT model and RTL Implementations
4.7. ARMCortexA5MPxnCT
4.7.1. Ports
4.7.2. Additional protocols
4.7.3. Parameters
4.7.4. Registers
4.7.5. Caches
4.7.6. Debug features
4.7.7. Verification and testing
4.7.8. Performance
4.7.9. Library dependencies
4.7.10. Differences between the CT model and RTL implementations
4.8. ARMCortexA5CT
4.8.1. Ports
4.8.2. Additional protocols
4.8.3. Parameters
4.8.4. Registers
4.8.5. Caches
4.8.6. Debug features
4.8.7. Verification and testing
4.8.8. Performance
4.8.9. Library dependencies
4.8.10. Differences between the CT model and RTL implementations
4.9. ARMCortexR7MPxnCT
4.9.1. Ports
4.9.2. Additional protocols
4.9.3. Parameters
4.9.4. Registers
4.9.5. Caches
4.9.6. Debug features
4.9.7. Verification and testing
4.9.8. Performance
4.9.9. Library dependencies
4.9.10. Differences between the CT model and RTL implementations
4.10. ARMCortexR5CT
4.10.1. Ports
4.10.2. Additional protocols
4.10.3. Parameters
4.10.4. Registers
4.10.5. Caches
4.10.6. Debug Features
4.10.7. Verification and Testing
4.10.8. Performance
4.10.9. Library dependencies
4.10.10. Differences between the CT model and RTL Implementations
4.11. ARMCortexR4CT
4.11.1. Ports
4.11.2. Additional protocols
4.11.3. Parameters
4.11.4. Registers
4.11.5. Caches
4.11.6. Debug features
4.11.7. Verification and testing
4.11.8. Performance
4.11.9. Library dependencies
4.11.10. Differences between the CT model and RTL implementations
4.12. ARM CortexM4CT
4.12.1. Ports
4.12.2. Additional protocols
4.12.3. Parameters
4.12.4. Registers
4.12.5. Caches
4.12.6. Debug features
4.12.7. Verification and testing
4.12.8. Performance
4.12.9. Library dependencies
4.12.10. Differences between the CT model and RTL implementations
4.13. ARMCortexM3CT
4.13.1. Ports
4.13.2. Additional protocols
4.13.3. Parameters
4.13.4. Registers
4.13.5. Caches
4.13.6. Debug features
4.13.7. Verification and testing
4.13.8. Performance
4.13.9. Library dependencies
4.13.10. Differences between the CT model and RTL implementations
4.14. ARMv7A - AEM
4.14.1. Ports
4.14.2. Additional protocols
4.14.3. Parameters
4.14.4. Registers
4.14.5. Caches
4.14.6. Debug Features
4.14.7. Verification and Testing
4.14.8. Performance
4.14.9. Library dependencies
4.14.10. Boundary features and architectural checkers
4.15. ARM1176CT
4.15.1. Ports
4.15.2. Additional protocols
4.15.3. Parameters
4.15.4. Registers
4.15.5. Debug features
4.15.6. Verification and testing
4.15.7. Performance
4.15.8. Library dependencies
4.15.9. Differences between the CT model and RTL implementations
4.16. ARM1136CT
4.16.1. Ports
4.16.2. Additional protocols
4.16.3. Parameters
4.16.4. Registers
4.16.5. Debug features
4.16.6. Verification and testing
4.16.7. Performance
4.16.8. Library dependencies
4.16.9. Differences between the CT model and RTL implementations
4.17. ARM968CT
4.17.1. Ports
4.17.2. Additional protocols
4.17.3. Parameters
4.17.4. Registers
4.17.5. Debug features
4.17.6. Verification and testing
4.17.7. Performance
4.17.8. Library dependencies
4.17.9. Differences between the CT model and RTL implementations
4.17.10. DMA
4.18. ARM926CT
4.18.1. Ports
4.18.2. Additional protocols
4.18.3. Parameters
4.18.4. Registers
4.18.5. Debug features
4.18.6. Verification and testing
4.18.7. Performance
4.18.8. Library dependencies
4.18.9. Differences between the CT model and RTL implementations
4.19. Implementation differences
4.19.1. Caches
4.19.2. CP14 Debug coprocessor
4.19.3. MicroTLB
4.19.4. TLB
4.19.5. Memory Access
4.19.6. Timing
4.19.7. VIC Port
4.20. Processor CADI Implementation of Optional Functionality
4.20.1. CADI Implementation
4.21. CADI interactions with processor behavior
4.22. Additional protocols
4.22.1. InstructionCount
5. Peripheral and Interface Components
5.1. About the components
5.2. PV Bus components
5.2.1. About the PVBus components
5.2.2. PVBusDecoder component
5.2.3. PVBusMaster component
5.2.4. PVBusRange component
5.2.5. PVBusSlave component
5.2.6. TZSwitch component
5.2.7. C++ classes
5.3. AMBA-PV Components
5.3.1. About the AMBA-PV components
5.3.2. AMBA-PV component protocols
5.3.3. PVBus2AMBAPV component
5.3.4. AMBAPV2PVBus component
5.3.5. PVBus2AMBAPVACE component
5.3.6. AMBAPVACE2PVBus component
5.3.7. SGSignal2AMBAPVSignal component
5.3.8. AMBAPVSignal2SGSignal component
5.3.9. SGStateSignal2AMBAPVSignalState component
5.3.10. AMBAPVSignalState2SGStateSignal component
5.3.11. SGValue2AMBAPVValue component
5.3.12. SGValue2AMBAPVValue64 component
5.3.13. AMBAPVValue2SGValue component
5.3.14. AMBAPVValue2SGValue64 component
5.3.15. SGValueState2AMBAPVValueState component
5.3.16. SGValueState2AMBAPVValueState64 component
5.3.17. AMBAPVValueState2SGValueState component
5.3.18. AMBAPVValueState2SGValueState64 component
5.4. Example Peripheral Components
5.4.1. About the Example Peripheral Components Model Library
5.4.2. PL011_Uart component
5.4.3. SerialCrossover component
5.4.4. TelnetTerminal component
5.4.5. PL022_SSP component
5.4.6. PL030_RTC component
5.4.7. PL031_RTC component
5.4.8. PL041_AACI component
5.4.9. AudioOut_File component
5.4.10. AudioOut_SDL component
5.4.11. PL050_KMI_component
5.4.12. PS2Keyboard component
5.4.13. PS2Mouse component
5.4.14. PL061_GPIO component
5.4.15. PL080_DMAC component
5.4.16. PL110_CLCD component
5.4.17. PL111_CLCD component
5.4.18. PL180_MCI component
5.4.19. MMC component
5.4.20. PL192_VIC component
5.4.21. PL310_L2CC component
5.4.22. PL330_DMAC component
5.4.23. PL340_DMC component
5.4.24. PL350_SMC component
5.4.25. PL350_SMC_NAND_FLASH component
5.4.26. PL390_GIC component
5.4.27. SP804_Timer component
5.4.28. SP805_Watchdog component
5.4.29. SP810_SysCtrl component
5.4.30. TZIC component
5.4.31. TZMPU component
5.4.32. RemapDecoder
5.4.33. BP135_AXI2APB component
5.4.34. BP141_TZMA component
5.4.35. BP147_TZPC component
5.4.36. AndGate component
5.4.37. OrGate component
5.4.38. ICS307 component
5.4.39. ElfLoader component
5.4.40. FlashLoader component
5.4.41. IntelStrataFlashJ3 component
5.4.42. VFS2 component
5.4.43. MessageBox component
5.4.44. RAMDevice component
5.4.45. SMSC_91C111 component
5.4.46. HostBridge component
5.4.47. VirtualEthernetCrossover
5.4.48. CCI400 component
5.4.49. GIC400
5.4.50. MemoryMappedCounterModule
5.5. Visualization Library
5.5.1. About the Visualisation library
5.5.2. LCD protocol
5.5.3. Visualisation components
5.5.4. GUIPoll component
5.5.5. C++ classes
5.6. Using Component Features
5.6.1. Terminal
5.6.2. User mode networking
5.6.3. Setting-up a TAP network connection and configuring the networking environment for Microsoft Windows
5.6.4. Setting-up a network connection and configuring the networking environment for Linux
5.7. CADI sync watchpoints
5.8. Non-CADI sync watchpoints
5.8.1. Controlling and observing the syncLevel
5.9. SCADI
5.9.1. Intended use of CADI and SCADI
5.9.2. Responsibilities of the SCADI caller
5.9.3. Obtaining the SCADI interface
5.9.4. SCADI semantics
6. Versatile Express Model: Platform and Components
6.1. About the Versatile Express baseboard components
6.2. VE model memory map
6.3. VE model parameters
6.3.1. Switch S6
6.4. VEVisualisation component
6.4.1. Ports
6.4.2. Additional protocols
6.4.3. Parameters
6.4.4. Registers
6.4.5. Debug Features
6.4.6. Verification and testing
6.4.7. Performance
6.4.8. Library dependencies
6.5. VE_SysRegs component
6.5.1. Ports
6.5.2. Additional protocols
6.5.3. Parameters
6.5.4. Registers
6.5.5. Debug Features
6.5.6. Verification and testing
6.5.7. Performance
6.5.8. Library dependencies
6.6. Other VE model components
6.6.1. VEConnector and VESocket components
6.6.2. VEInterruptForwarder component
6.6.3. VERemapper component
6.7. Differences between the VE hardware and the system model
6.7.1. Memory map
6.7.2. Memory aliasing
6.7.3. Features not present in the model
6.7.4. Features partially implemented in the model
6.7.5. Restrictions on the processor models
6.7.6. Timing considerations
7. Emulation Baseboard Model: Platform and Components
7.1. About the Emulation Baseboard components
7.2. Emulation Baseboard memory map
7.3. Emulation Baseboard parameters
7.3.1. Switch S6
7.3.2. Switch S8
7.4. EBVisualisation component
7.4.1. Ports
7.4.2. Additional protocols
7.4.3. Parameters
7.4.4. Registers
7.4.5. Debug Features
7.4.6. Verification and testing
7.4.7. Performance
7.4.8. Library dependencies
7.5. EB_SysRegs component
7.5.1. Ports
7.5.2. Additional protocols
7.5.3. Parameters
7.5.4. Registers
7.5.5. Debug Features
7.5.6. Verification and testing
7.5.7. Performance
7.5.8. Library dependencies
7.6. EBCortexA9_SysRegs component
7.6.1. Ports
7.6.2. Additional protocols
7.6.3. Parameters
7.6.4. Registers
7.6.5. Debug Features
7.6.6. Verification and testing
7.6.7. Performance
7.6.8. Library dependencies
7.7. TSC2200 component
7.7.1. Ports
7.7.2. Additional protocols
7.7.3. Parameters
7.7.4. Registers
7.7.5. Debug Features
7.7.6. Verification and testing
7.7.7. Performance
7.7.8. Library dependencies
7.7.9. Functionality
7.8. Other Emulation Baseboard components
7.8.1. EBConnector and EBSocket components
7.8.2. EBInterruptForwarder component
7.8.3. EBRemapper component
7.9. Differences between the EB hardware and the system model
7.9.1. Features not present in the model
7.9.2. Remapping and DRAM aliasing
7.9.3. Dynamic memory characteristics
7.9.4. Status and system control registers
7.9.5. Generic Interrupt Controller
7.9.6. GPIO2
7.9.7. Timing considerations
8. Microcontroller Prototyping System: Platform and Components
8.1. About the Microcontroller Prototyping System components
8.2. MPS model memory map
8.2.1. MPS registers
8.3. MPSVisualisation
8.3.1. Ports
8.3.2. Additional protocols
8.3.3. Parameters
8.3.4. Registers
8.3.5. Debug features
8.3.6. Verification and testing
8.3.7. Performance
8.3.8. Library dependencies
8.4. MPS_CharacterLCD
8.4.1. Ports
8.4.2. Additional protocols
8.4.3. Parameters
8.4.4. Registers
8.4.5. Debug features
8.4.6. Verification and testing
8.4.7. Performance
8.4.8. Library dependencies
8.5. MPS_DUTSysReg
8.5.1. Ports
8.5.2. Additional protocols
8.5.3. Parameters
8.5.4. Registers
8.5.5. Debug features
8.5.6. Verification and testing
8.5.7. Performance
8.5.8. Library dependencies
8.6. Other MPS virtual platform components
8.6.1. MPSInterruptForwarder and MPSInterruptReceiver components
8.7. Differences between the MPS hardware and the system model
8.7.1. Features not present in the model
8.7.2. Timing considerations
A. AEM ARMv7-A specifics
A.1. Boundary features and architectural checkers
A.1.1. Aggressively pre-fetching TLB
A.1.2. Passive infinite TLB
A.1.3. Infinite write buffer
A.1.4. Treat cache invalidate operation as clean and invalidate
A.1.5. Cache incoherence check
A.1.6. Delayed operation of CP15 instructions
A.1.7. An undefined instruction failed its condition code check
A.1.8. Memory marking check
A.1.9. Memory operation reordering
A.1.10. Other checks
A.2. Debug architecture support
A.2.1. Invasive debug
A.2.2. Non-invasive debug
A.2.3. Debug registers
A.3. IMPLEMENTATION DEFINED features
A.3.1. ACTLR
A.3.2. TLB lockdown
A.3.3. Internal peripherals
A.4. Trace
A.4.1. TarmacTraceAEM

List of Figures

3.1. MasterClock in System Canvas
3.2. ClockDivider in System Canvas
3.3. ClockTimer in System Canvas
3.4. ClockTimer64 in System Canvas
4.1. ARMCortexA15CT in System Canvas
4.2. ARMCortexA9MPCT in System Canvas
4.3. ARMCortexA9UPCT in System Canvas
4.4. ARMCortexA8CT in System Canvas
4.5. ARMCortexA7CT in System Canvas
4.6. ARMCortexA5MPCT in System Canvas
4.7. ARMCortexA5CT in System Canvas
4.8. ARMCortexR7MPCT in System Canvas
4.9. ARMCortexR5CT in System Canvas
4.10. ARMCortexR4CT in System Canvas
4.11. ARMCortexM4CT in System Canvas
4.12. ARMCortexM3CT in System Canvas
4.13. ARMAEMv7AMPCT in System Canvas
4.14. CPU-cache architecture configuration - Example 1
4.15. CPU-cache architecture configuration - Example 2
4.16. ARM1176CT in System Canvas
4.17. ARM1136CT in System Canvas
4.18. ARM968CT in System Canvas
4.19. ARM926CT in System Canvas
5.1. Sample bus topology
5.2. PVBusDecoder in System Canvas
5.3. PVBusMaster in System Canvas
5.4. PVBusRange in System Canvas
5.5. PVBusSlave in System Canvas
5.6. TZSwitch in System Canvas
5.7. PVBus2AMBAPV in System Canvas
5.8. AMBAPV2PVBus in System Canvas
5.9. PVBus2AMBAPVACE in System Canvas
5.10. AMBAPV2PVBus in System Canvas
5.11. SGSignal2AMBAPVSignal in System Canvas
5.12. AMBAPVSignal2SGSignal in System Canvas
5.13. SGStateSignal2AMBAPVSignalState in System Canvas
5.14. AMBAPVSignalState2SGStateSignal in System Canvas
5.15. SGValue2AMBAPVValue in System Canvas
5.16. SGValue2AMBAPVValue64 in System Canvas
5.17. AMBAPVValue2SGValue in System Canvas
5.18. AMBAPVValue2SGValue64 in System Canvas
5.19. SGValueState2AMBAPVValueState in System Canvas
5.20. SGValueState2AMBAPVValueState64 in System Canvas
5.21. AMBAPVValue2SGValue in System Canvas
5.22. AMBAPVValue2SGValue64 in System Canvas
5.23. PL011_Uart in System Canvas
5.24. SerialCrossover in System Canvas
5.25. TelnetTerminal in System Canvas
5.26. PL022_SSP in System Canvas
5.27. PL030_RTC in System Canvas
5.28. PL031_RTC in System Canvas
5.29. PL041_AACI in System Canvas
5.30. AudioOut in System Canvas
5.31. AudioOut_SDL in System Canvas
5.32. Keyboard/Mouse controller in System Canvas
5.33. PS2Keyboard in System Canvas
5.34. PS2Mouse component in System Canvas
5.35. PL061_GPIO in System Canvas
5.36. PL080_DMAC in System Canvas
5.37. PL110_CLCD in System Canvas
5.38. PL111_CLCD in System Canvas
5.39. PL180_MCI in System Canvas
5.40. MMC in System Canvas
5.41. PL192_VIC in System Canvas
5.42. PL310_L2CC in System Canvas
5.43. PL310_L2CC in an example system
5.44. PL330_DMAC in System canvas
5.45. PL340_DMC in System Canvas
5.46. PL350_SMC in System Canvas
5.47. PL350_SMC_NAND_FLASH in System Canvas
5.48. PL390_GIC in System Canvas
5.49. SP804_Timer in System Canvas
5.50. SP805_Watchdog in System Canvas
5.51. SP810_SysCtrl in System Canvas
5.52. TZIC in System Canvas
5.53. TZMPU in System Canvas
5.54. RemapDecoder in System Canvas
5.55. BP135_AXI2APB in System Canvas
5.56. BP141_TZMA in System Canvas
5.57. BP147_TZPC in System Canvas
5.58. AndGate in System Canvas
5.59. OrGate in System Canvas
5.60. ICS307 in System Canvas
5.61. ElfLoader in System Canvas
5.62. FlashLoader in System Canvas
5.63. IntelStrataFlashJ3 in System Canvas
5.64. VFS2 in System Canvas
5.65. MessageBox component in System Canvas
5.66. RAMDevice in System Canvas
5.67. SMSC_91C111 in System Canvas
5.68. HostBridge in System Canvas
5.69. VirtualEthernetCrossover in System Canvas
5.70. CCI400 in System Canvas
5.71. GIC400 in System Canvas
5.72. MemoryMappedCounterModule in System Canvas
5.73. GUIPoll in System Canvas
5.74. Terminal block diagram
6.1. VE Real-Time System Model CLCD visualization window
6.2. VE RTSM CLCD with brot.axf image
6.3. VEVisualisation in System Canvas
6.4. VE_SysRegs in System Canvas
7.1. EB Real-Time System Model CLCD visualization window
7.2. EB RTSM CLCD with brot.axf image
7.3. EBVisualisation in System Canvas
7.4. EB_SysRegs in System Canvas
7.5. EBCortexA9_SysRegs in System Canvas
7.6. TSC2200 in System Canvas
8.1. MPSVirtualisation component in sgcanvas
8.2. Microprocessor Prototyping System Real-Time System Model CLCD
8.3. MPSVirtualisation component in sgcanvas
8.4. MPS_DUTSysReg component in sgcanvas

List of Tables

2.1. Parameters to control functional cache behavior
3.1. MasterClock ports
3.2. ClockDivider ports
3.3. ClockDivider configuration parameters
3.4. ClockTimer ports
3.5. ClockTimer ports
4.1. ARMCortexA15xnCT ports
4.2. ARMCortexA15xnCT parameters
4.3. ARMCortexA15xnCT individual processor parameters
4.4. ARMCortexA9MPxnCT ports
4.5. ARMCortexA9MPxnCT parameters
4.6. ARMCortexA9MPxnCT individual processor parameters
4.7. ARMCortexA9UPCT ports
4.8. ARMCortexA9UPCT parameters
4.9. ARMCortexA9UPCT individual processor parameters
4.10. ARMCortexA8CT ports
4.11. ARMCortexA8CT parameters
4.12. ARMCortexA7xnCT ports
4.13. ARMCortexA7xnCT parameters
4.14. ARMCortexA7xnCT individual processor parameters
4.15. ARMCortexA5MPxnCT ports
4.16. ARMCortexA5MPxnCT parameters
4.17. ARMCortexA5MPxnCT individual processor parameters
4.18. ARMCortexA5CT ports
4.19. ARMCortexA5CT parameters
4.20. ARMCortexA5CT individual processor parameters
4.21. ARMCortexR7MPxnCT ports
4.22. ARMCortexR7MPxnCT parameters
4.23. ARMCortexR7MPxnCT individual processor parameters
4.24. ARMCortexR5CT ports
4.25. ARMCortexR5CT parameters
4.26. ARMCortexR5CT individual processor parameters
4.27. ARMCortexR4CT ports
4.28. ARMCortexR4CT parameters
4.29. ARMCortexM4CT ports
4.30. ARMCortexM4CT parameters
4.31. ARMCortexM3CT ports
4.32. ARMCortexM3CT parameters
4.33. ARMAEMv7AMPCT ports
4.34. Multiprocessing parameters
4.35. Processor configuration parameters
4.36. Memory configuration parameters
4.37. General cache configuration parameters
4.38. Cache block configuration parameters
4.39. Debug architecture configuration parameters
4.40. Core configuration parameters
4.41. Core configuration parameters
4.42. Message severity levels
4.43. Message configuration parameters
4.44. ARM1176CT ports
4.45. ARM1176CT parameters
4.46. ARM1136CT ports
4.47. ARM1136CT parameters
4.48. ARM968CT ports
4.49. ARM968CT parameters
4.50. ARM926CT ports
4.51. ARM926CT parameters
4.52. CADI Broker Implementation
4.53. CADI Target Implementation
4.54. Possible run state values
5.1. PVBus examples
5.2. PVBusDecoder ports
5.3. PVBusMaster ports
5.4. PVBusRange ports
5.5. PVBus ports
5.6. PVBusSlave configuration parameters
5.7. TZSwitch ports
5.8. TZSwitch configuration parameters
5.9. PVBus2AMBAPV ports
5.10. PVBus2AMBAPV configuration parameters
5.11. AMBAPV2PVBus component ports
5.12. AMBAPV2PVBus configuration parameters
5.13. PVBus2AMBAPVACE ports
5.14. PVBus2AMBAPVACE configuration parameters
5.15. PVBus2AMBAPV ports
5.16. SGSignal2AMBAPVSignal ports
5.17. AMBAPVSignal2SGSignal component ports
5.18. SGStateSignal2AMBAPVSignalState ports
5.19. AMBAPVSignalState2SGStateSignal component ports
5.20. SGValue2AMBAPVValue ports
5.21. SGValue2AMBAPVValue64 ports
5.22. AMBAPVValue2SGValue component ports
5.23. AMBAPVValue2SGValue64 component ports
5.24. SGValueState2AMBAPVValueState ports
5.25. SGValueState2AMBAPVValueState64 ports
5.26. AMBAPVValueState2SGValueState component ports
5.27. AMBAPVValueState2SGValueState64 component ports
5.28. PL011_Uart ports
5.29. Bits for dataTransmit()
5.30. Bits for dataReceive()
5.31. Bits for signalsSet()
5.32. Bits for signalsGet()
5.33. PL011_Uart configuration parameters
5.34. PL011_Uart registers
5.35. SerialCrossover ports
5.36. TelnetTerminal ports
5.37. TelnetTerminal configuration parameters
5.38. PL022_SSP ports
5.39. PL022_SSP registers
5.40. PL030_RTC ports
5.41. PL030_RTC registers
5.42. PL031_RTC ports
5.43. PL031_RTC registers
5.44. PL041_AACI ports
5.45. PL041_AACI registers
5.46. AudioOut_File ports
5.47. AudioOut_File configuration parameters
5.48. AudioOut_SDL ports
5.49. PL050_KMI ports
5.50. PL050_KMI registers
5.51. PS2Keyboard ports
5.52. PS2Mouse ports
5.53. PL061_GPIO ports
5.54. PL061_GPIO registers
5.55. PL080_DMAC ports
5.56. PL080_DMAC configuration parameters
5.57. PL080_DMAC registers
5.58. PL110_CLCD ports
5.59. PL110_CLCD configuration parameters
5.60. PL110_CLCD registers
5.61. PL111_CLCD ports
5.62. PL111_CLCD configuration parameters
5.63. PL111_CLCD registers
5.64. PL180_MCI ports
5.65. PL180_MCI registers
5.66. MMC ports
5.67. MMC configuration parameters
5.68. MMC registers
5.69. PL192_VIC ports
5.70. PL192_VIC registers
5.71. PL310_L2CC ports
5.72. PL310_L2CC configuration parameters
5.73. PL310_L2CC registers
5.74. PL330_DMAC ports
5.75. PL330_DMAC configuration parameters
5.76. PL330_DMAC registers
5.77. PL340_DMC ports
5.78. PL340_DMC configuration parameters
5.79. PL340_DMC registers
5.80. PL350_SMC ports
5.81. PL350_SMC configuration parameters
5.82. PL350_SMC registers
5.83. PL350_SMC_NAND_FLASH ports
5.84. PL350_SMC_NAND_FLASH configuration parameters
5.85. PL390_GIC ports
5.86. PL390_GIC configuration parameters
5.87. PL 390_GIC registers: Distributor Interface
5.88. SP804_Timer ports
5.89. SP804_Timer registers
5.90. SP805_Watchdog ports
5.91. SP805_Watchdog configuration parameters
5.92. SP805_Watchdog registers
5.93. SP810_SysCtrl ports
5.94. SP810_SysCtrl configuration parameters
5.95. SP810_SysCtrl registers
5.96. TZIC ports
5.97. TZIC registers
5.98. TZMPU ports
5.99. TZMPU configuration parameters
5.100. TZMPU registers
5.101. RemapDecoder ports
5.102. BP135_AXI2APB ports
5.103. BP141_TZMA security control
5.104. BP141_TZMA ports
5.105. BP141_TZMA configuration parameters
5.106. BP147_TZPC ports
5.107. BP147_TZPC registers
5.108. AndGate ports
5.109. OrGate ports
5.110. od to scale conversion
5.111. ICS307 ports
5.112. ICS307 configuration parameters
5.113. ElfLoader ports
5.114. ElfLoader configuration parameters
5.115. FlashLoader ports
5.116. FlashLoader configuration parameters
5.117. IntelStrataFlashJ3 ports
5.118. IntelStrataFlashJ3 configuration parameters
5.119. VFS2 ports
5.120. VFS2 configuration parameters
5.121. MessageBox ports
5.122. MessageBox configuration parameters
5.123. MessageBox registers
5.124. RAMDevice ports
5.125. RAMDevice configuration parameters
5.126. SMSC_91C111 ports
5.127. SMSC_91C111 configuration parameters
5.128. SMSC_91C111 bank 0 registers
5.129. SMSC_91C111 bank 1 registers
5.130. SMSC_91C111 bank 2 registers
5.131. SMSC_91C111 bank 3 registers
5.132. HostBridge ports
5.133. HostBridge configuration parameters
5.134. VirtualEthernetCrossover ports
5.135. CCI400 ports
5.136. CCI400 configuration parameters
5.137. GIC400 ports
5.138. GIC400 configuration parameters
5.139. MemoryMappedCounterModule ports
5.140. MemoryMappedCounterModule configuration parameters
5.141. GUIPoll component ports
5.142. GUIPoll configuration parameters
6.1. Memory map
6.2. CS2 peripheral memory map for secure_memory option
6.3. CS2 peripheral memory map
6.4. CS3 peripheral memory map
6.5. VE model instantiation parameters
6.6. Default positions for VE System Model switch
6.7. STDIO redirection
6.8. VEVisualisation component ports
6.9. VEVisualisation configuration parameters
6.10. VE_SysRegs ports
6.11. VE_SysRegs configuration parameters
6.12. VE_SysRegs registers
7.1. Memory map and interrupts for standard peripherals
7.2. EB Baseboard Model instantiation parameters
7.3. Default positions for EB System Model switch S6
7.4. STDIO redirection
7.5. EB System Model switch S8 settings
7.6. EBVisualisation component ports
7.7. EBVisualisation configuration parameters
7.8. EB_SysRegs ports
7.9. EB_SysRegs configuration parameters
7.10. EB_SysRegs registers
7.11. EBCortexA9_SysRegs ports
7.12. EBCortexA9_SysRegs registers
7.13. TSC2200 ports
7.14. TSC2200 configuration parameters
8.1. Overview of MPS memory map
8.2. MPS CPU system registers
8.3. MPS DUT system registers
8.4. MPS LCD registers
8.5. Memory configuration
8.6. User switches
8.7. Seven-segment register
8.8. MPSVisualisation interactive controls
8.9. MPSVisualisation component ports
8.10. MPSVisualisation configuration parameters
8.11. MPS_CharacterLCD component ports
8.12. MPS_CharacterLCD registers
8.13. MPS_DUTSysReg ports
8.14. MPS_DUTSysReg configuration parameters
8.15. MPS_DUTSysReg registers
A.1. Delayed CP15 operations
A.2. Internal peripherals
A.3. Internal peripherals (use_Cortex-A15_peripherals)

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A15 February 2008New document, based on previous documentation.
Revision BJune 2008Update for System Generator 4.0.
Revision CAugust 2008Update for System Generator 4.0 SP1.
Revision DDecember 2008Update for Fast Models 4.1.
Revision EMarch 2009Update for Fast Models 4.2. Combined all Fast Model Portfolio components into one manual.
Revision FMay 2009Update for Fast Models 5.0.
Revision GSeptember 2009Update for Fast Models 5.1
Revision HFebruary 2010Update for Fast Models 5.2
Revision IOctober 2010Update for Fast Models 6.0.
Revision JMay 2011Update for Fast Models 6.1.
Revision KJuly 2011Update for Fast Models v6.2.
Revision LNovember 2011Update for Fast Models v7.0.
Revision MMay 2012Update for Fast Models v7.1.
Copyright © 2008-2012 ARM. All rights reserved.ARM DUI 0423M
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