5.4.24. PL350_SMC component

The PL350_SMC component is a programmer’s view model of the ARM PL350 Static Memory Controller (SMC). It provides two memory interfaces. Each interface can be connected to a maximum of four memory devices, giving a total of eight inputs from the PVBusDecoder and eight outputs to either SRAM or NAND devices. Only one kind of memory can be connected to a particular interface, either SRAM or NAND. Further technical details on the SMC are described elsewhere. See the ARM PrimeCell Static Memory Controller (PL350 series) Technical Reference Manual.

The PL350_SMC component implementation provides a PVBus slave to control the device behavior. A remap port is also provided to assist in remapping particular memory regions.

Figure 5.46 shows a view of the component in System Canvas.

Figure 5.46. PL350_SMC in System Canvas

PL350_SMC in System Canvas

This component is written in LISA+.

Ports

Table 5.80 provides a brief description of the ports for the PL350_SMC component. For more information, see the component documentation. See ARM PrimeCell Static Memory Controller (PL350 series) Technical Reference Manual.

Table 5.80. PL350_SMC ports

NamePort protocolTypeDescription
axi_chip_if0_in[4]PVBusSlaveSlave bus for interface 0 connecting to memory
axi_chip_if1_in[4]PVBusSlaveSlave bus for interface 1 PVBus connecting to memory
apb_interfacePVBusSlaveSlave bus interface for register access
axi_chip_if0_out[4]PVBusMasterMaster interface 0 to connect to SRAM/NAND
axi_chip_if1_out[4]PVBusMasterMaster interface 1 to connect to SRAM/NAND
axi_remapPVBusSlaveRemaps the device to 0x0
irq_in_if0SignalSlaveInterface 0 interrupt connection from the device
irq_in_if1SignalSlaveInterface 1 interrupt connection from the device
nand_remap_portPVBusSlaveRemaps the connected NAND port to 0x0
irq_outSignalMasterInterrupt port

Additional protocols

The PL350_SMC component has no additional protocols.

Parameters

Table 5.81 provides a description of the configuration parameters for the PL350_SMC component.

Table 5.81. PL350_SMC configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value

IF0_MEM_TYPE_PARAMETER

IF1_MEM_TYPE_PARAMETER

Indicates memory type for interfaces 0 and 1:

0

SRAM

1

NAND.

Integer0, 10
REMAP

Indicates if a particular interface has been remapped:

-1

remap not enabled

0 to 7

identifies device that gets address 0x0.

Integer-1, 0-7-1

IF0_CHIP_0 to IF0_CHIP_3

IF1_CHIP_0 to IF1_CHIP_3

Indicates memory connected to chip slots for interfaces 0 and 1:

True

nothing connected to the interface

False

memory connected.

BooleanTrue, FalseFalse

IF0_CHIP0_BASE to IF0_CHIP3_BASE

IF1_CHIP0_BASE to IF1_CHIP3_BASE

Chip y base address for interfaces 0 and 1.

Integeraddress where chips connected0

IF0_CHIP0_SIZE to IF0_CHIP3_SIZE

IF1_CHIP0_SIZE to IF1_CHIP3_SIZE

Chip y size for interfaces 0 and 1.

Integerdevice size0

Registers

Table 5.82 provides a description of the configuration registers for the PL350_SMC component. These are accessible through the APB interface.

Table 5.82. PL350_SMC registers

Register nameOffsetAccessDescription
memc_status0x000read onlyMemory controller status register
memif_cfg0x004read onlyMemory interface configuration register
memc_cfg_set0x008write onlyUsed to set memory controller configurations
memc_cfg_clr0x00Cwrite onlyClear the configuration register
direct_cmd0x010write onlyCommands sent to the device
set_cycles0x014write onlyHolding register for cycle settings
set_opmode0x018write onlyHolding register for opmode settings
refresh_period_00x020read/writeInsert idle cycles on interface 0
refresh_period_10x024read/writeInsert idle cycles on interface 1
device_cycles0_00x100read onlyDevice cycle configuration
device_cycles0_10x120read onlyDevice cycle configuration
device_cycles0_20x140read onlyDevice cycle configuration
device_cycles0_30x160read onlyDevice cycle configuration
device_cycles1_00x180read onlyDevice cycle configuration
device_cycles1_10x1A0read onlyDevice cycle configuration
device_cycles1_20x1C0read onlyDevice cycle configuration
device_cycles1_30x1E0read onlyDevice cycle configuration
opmode0_00x104read onlyOpmode configuration
opmode0_10x124read onlyOpmode configuration
opmode0_20x144read onlyOpmode configuration
opmode0_30x164read onlyOpmode configuration
opmode1_00x184read onlyOpmode configuration
opmode1_10x1A4read onlyOpmode configuration
opmode1_20x1C4read onlyOpmode configuration
opmode1_30x1E4read onlyOpmode configuration
user_status0x200read/writeUser status register
user_config0x204read/writeUser configuration register
periph_id_00xFE0read onlyPeripheral ID register 0[a]
periph_id_10xFE4read onlyPeripheral ID register 1[a]
periph_id_20xFE8read onlyPeripheral ID register 2[a]
periph_id_30xFECread onlyPeripheral ID register 3[a]
pcell_id_00xFF0read onlyPrimeCell ID register 0[a]
pcell_id_10xFF4read onlyPrimeCell ID register 1[a]
pcell_id_20xFF8read onlyPrimeCell ID register 2[a]
pcell_id_30xFFCread onlyPrimeCell ID register 3[a]

[a] This register has no CADI interface.


Debug features

The PL350_SMC component has no debug features.

Verification and testing

The functions of the PL350_SMC component have been tested individually using a tailored test suite.

Performance

The PL350_SMC component is optimized to have negligible impact on transaction performance, except when memory remap settings are changed when there might be a significant effect.

Library dependencies

The PL350_SMC component has no dependencies on external libraries.

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