5.4.14. PL061_GPIO component

The General Purpose Input/Output (GPIO) component is a programmer’s view model of the ARM PL061 PrimeCell. It provides eight programmable inputs or outputs. Ports of different widths can be created by multiple instantiation. In addition, an interrupt interface is provided to configure any number of pins as interrupt sources. For more information, see the component documentation. See ARM PrimeCell General Purpose Input/Output (PL061) Technical Reference Manual.

Figure 5.35 shows a view of the component in System Canvas.

Figure 5.35. PL061_GPIO in System Canvas

PL061_GPIO in System Canvas

This component is written in LISA+.


Table 5.53 provides a brief description of the PL061_GPIO ports. For more information, see the component documentation.

Table 5.53. PL061_GPIO ports

NamePort protocolTypeDescription
pvbusPVBusSlaveSlave port for connection to PV bus master/decoder.
GPIO_InValueSlaveInput lines[a].
GPIO_OutValueMasterOutput lines[a].
GPIO_IntrSignalMasterInterrupt signal indicating to an interrupt controller that an interrupt occurred in one or more of the GPIO_In lines.
GPIO_MISValueMasterIndicates the masked interrupt status[a].

[a] Only the lower end eight bits [7:0] are used.

Additional protocols

The PL061_GPIO component has no additional protocols.


The PL061_GPIO component has no parameters.


Table 5.54 provides a description of the configuration registers for the PL061_GPIO component.

Table 5.54. PL061_GPIO registers

Register nameOffsetAccessDescription
GPIODATA0x000 - 0x3FCread/writeGPIO prime data register. The address offsets serve as a mask. Only bits [11:2] are valid as the mask.[a]
GPIODIR0x400read/writeData direction register. Set for output, clear for input.
GPIOIS0x404read/writeInterrupt sense register. Set for level trigger, clear for edge trigger.
GPIOIBE0x408read/writeBits set, both edges on corresponding pin trigger and interrupt.
GPIOIEV0x40Cread/writeInterrupt event register. Bit set for rising edge or high level trigger.
GPIOIE0x410read/writeInterrupt mask register.
GPIORIS0x414readRaw interrupt status register.
GPIOMIS0x418readMasked interrupt status register.
GPIOIC0x41CwriteInterrupt clear register.
GPIOAFSEL0x420read/writeMode control select
GPIOPeriphID00xfe0readPeripheral ID register
GPIOPeriphID10xfe4readPeripheral ID register
GPIOPeriphID20xfe8readPeripheral ID register
GPIOPeriphID30xfecreadPeripheral ID register
GPIOPCellID00xff0readPrimeCell ID register
GPIOPCellID10xff4readPrimeCell ID register
GPIOPCellID20xff8readPrimeCell ID register
GPIOPCellID30xffcreadPrimeCell ID register

[a] For writes, values written to the registers are transferred onto the GPOIT pins if the respective pins have been configured as output ports. Set certain pins in GPIO_Mask to high to enable writing. A similar process applies to reads. Details of how to use this register are covered elsewhere. See the ARM PrimeCell General Purpose Input/Output (PL061) Technical Reference Manual.

Debug features

The PL061_GPIO component has no debug features.

Verification and testing

The functions of the PL061_GPIO component have been tested individually using a tailored test suite.


The PL061_GPIO component is not expected to significantly affect the performance of a PV system.

Library dependencies

The PL061_GPIO component has no dependencies on external libraries.

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