5.4.5. PL022_SSP component


The PL022_SSP component is a preliminary release. It is provided as-is with the VE reference platform model, and is not yet a fully supported peripheral.

The PL022_SSP component is a programmer’s view model of the ARM PL022 Synchronous Serial Port (SSP) PrimeCell. Although the PL022_SSP component has clock input, it is not internally clock-driven. This is different to the equivalent hardware.

For more information, see the component documentation. See the ARM PrimeCell Synchronous Serial Port (PL022) Technical Reference Manual.

Figure 5.26 shows a view of the component in System Canvas.

Figure 5.26. PL022_SSP in System Canvas

PL022_SSP in System Canvas

This component is written in LISA+.


Table 5.38 provides a brief description of the PL022_SSP ports. For more information, see the component documentation.

Table 5.38. PL022_SSP ports

NamePort protocolTypeDescription
clkClockSignalSlaveMain PrimeCell SSP clock input.
clkinClockSignalSlavePrimeCell SSP clock input.
pvbusPVBusSlaveSlave port for connection to PV bus master/decoder.
rxdValueStateSlavePrimeCell SSP receive data.
clkoutClockSignalMasterClock output.
intrSignalMasterInterrupt signaling.
rorintrSignalMasterReceive overrun interrupt.
rtintrSignalMasterReceive timeout interrupt[a].
rx_dma_portPL080_DMAC_DmaPortProtocol[b]MasterPrimeCell SSP receive DMA port.
rxintrSignalMasterReceive FIFO service request port.
tx_dma_portPL080_DMAC_DmaPortProtocol[b]MasterPrimeCell SSP transmit DMA port.
txdValueStateMasterPrimeCell SSP transmit data.
txintrSignalMasterTransmit FIFO service request.

[a] Not supported.

Additional protocols

The PL022_SSP component has no additional protocols.


The PL022_SSP component has no parameters.


Table 5.39 provides a description of the configuration registers for the PL022_SSP component.

Table 5.39. PL022_SSP registers

Register nameOffsetAccessDescription
SSPCR00x000read/writeControl register 0.
SSPCR10x004read/writeControl register 1.
SSPDR0x008read/writeFIFO data.
SSPSR0x00Cread onlyStatus.
SSPCPSR0x010read/writeClock prescale.
SSPIMSC0x014read/writeInterrupt mask set/clear.
SSPRIS0x018read onlyRaw interrupt status.
SSPMIS0x01Cread onlyMasked interrupt status.
SSPICR0x020write onlyInterrupt clear.
SSPDMACR0x024read/writeDMA control.
SSPeriphID00xFE0read onlyPeripheral ID bits 7:0.
SSPeriphID10xFE4read onlyPeripheral ID bits 15:8.
SSPeriphID20xFE8read onlyPeripheral ID bits 23:16.
SSPeriphID30xFECread onlyPeripheral ID bits 31:24.
SSPPCellID00xFF0read onlyPrimeCell ID bits 7:0.
SSPPCellID010xFF4read onlyPrimeCell ID bits 15:8.
SSPPCellID0xFF8read onlyPrimeCell ID bits 23:16.
SSPPCellID30xFFCread onlyPrimeCell ID bits 31:24.

Debug features

The PL022_SSP component has no debug features.

Verification and testing

The functions of the PL022_SSP component have been tested individually using a tailored test suite. The component has not been validated against a target operating system, but improved support is expected in the next release.


The PL022_SSP component is not expected to significantly affect the performance of a PV system.

Library dependencies

The PL022_SSP component has no dependencies on external libraries.

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