5.4.48. CCI400 component

The CCI400 component is the Cache Coherent Interconnect for AXI 4. AXI Coherency Extensions (ACE) are extensions to AXI4 that provide support for system-level cache-coherency between multiple clusters. See Figure 5.70:

Figure 5.70. CCI400 in System Canvas

CCI400 in System Canvas

This component is written in LISA+.

Ports

Table 5.135 provides a brief description of the CCI400 component ports. For more information, see the hardware documentation.

Table 5.135. CCI400 ports

NamePort ProtocolTypeDescription
acchannelenValueslaveFor each upstream port, determine if it is enabled or not with.respect to snoop requests.
barrierterminateValueslaveFor each downstream port, determine if barriers are terminated at that port.
broadcastcachemainValueslaveFor each downstream port, determine if broadcast cache maintenance operations are forwarded down that port.
bufferableoverrideValueslaveFor each downstream port, determine if all transactions are forced to non-bufferable.
errorirqSignalmasterA signal stating that the imprecise error register is nonzero.
evntcntoverflow[5]SignalmasterWhen an event counter overflows, it sets the corresponding signal.
lint_ace_3_reset_state, lint_ace_4_reset_stateSignalslaveThese ports can be connected to the reset signals of the system attached to the pbvus_s_ace_3 and pvbus_s_ace_4 ports.
pvbus_mPVBusmasterMaster port for all downstream memory accesses.
pbvus_s_ace_3, pvbus_s_ace_4PVBusslaveACE-capable slave ports.
pvbus_s_ace_lite_plus_dvm_0, pvbus_s_ace_lite_plus_dvm_1, pvbus_s_ace_lite_plus_dvm_2PVBusslaveMemory bus interface that implements ACE lite and DVM protocol.
reset_inSignalslaveSignal to reset the CCI.

Additional protocols

The CCI400 component has no additional protocols.

Parameters

Table 5.136 provides a description of the configuration parameters for the CCI400 component.

Table 5.136. CCI400 configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
acchannelenFor each upstream port, determine if it is enabled or not with respect to snoop requests.Integer0-3131
barrierterminateFor each downstream port, determine if barriers are terminated at that port.Integer0-77
broadcastcachemainFor each downstream port a bit determines if broadcast cache maintenance operations are forwarded down that port.Integer0-70
bufferableoverrideFor each downstream port, determine if all transactions are forced to non-bufferable.Integer0-70
cache_state_modelledModel the cache coherency operations. This must be enabled to correctly maintain coherency between ACE masters that model cache state.Booleantrue or falsetrue
force_on_from_startThe CCI normally starts up with snooping disabled. However, using this permits the model to start up as enabled without having to program it. This is only set up at simulation reset and not at signal reset.Booleantrue or falsefalse
log_enabled

Enable log messages from the CCI register file:

  • 0 means do not print anything

  • 1 means print only access violations

  • 2 means also print writes

  • 3 means also print reads.

Integer0, 1, 2, 31

Registers

The CCI400 component provides the registers specified by the technical reference manual.

Debug Features

The CCI400 component exports a CADI debug interface.

Verification and testing

The CCI400 component has been tested:

  • by running a switching hypervisor on an example system containing an ARMCortexA7xnCT component and an ARMCortexA15xnCT CCI400 model.

Performance

If cache_state_modelled is disabled, the CCI400 component has negligible performance impact. If cache_state_modelled is enabled, it adds significant cost to throughput for coherent transactions.

Library dependencies

The CCI400 component has no dependencies on external libraries.

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