5.4.45. SMSC_91C111 component

The SMSC_91C111 component implements a model of the SMSC 91C111 Ethernet controller.

The model provides the register interface of the SMSC part and can be configured to act as an unconnected Ethernet port, or an Ethernet port connected to the host by an Ethernet bridge.

Information on how to install and configure the networking environment is described separately. See Setting-up a TAP network connection and configuring the networking environment for Microsoft Windows.

Figure 5.67 shows a view of the component in System Canvas.

Figure 5.67. SMSC_91C111 in System Canvas

SMSC_91C111 in System Canvas

This component is written in C++.

Ports

Table 5.126 provides a brief description of the ports in the SMSC_91C111 component.

Table 5.126. SMSC_91C111 ports

NamePort protocolTypeDescription
pvbusPVBusSlaveSlave port for connection to PV bus master/decoder.
intrSignalMasterInterrupt signaling.
clockClockSignalSlaveClock input, typically 25MHz, which sets the master transmit/receive rate.
ethVirtualEthernetMasterEthernet port.

Additional protocols

The SMSC_91C111 component has one additional protocol.

The VirtualEthernet protocol has the following behaviors:

sendToSlave(EthernetFrame* frame)

send an Ethernet frame to the slave port

sendToMaster(EthernetFrame* frame)

send an Ethernet frame to the master port.

The Ethernet frame class encapsulates an Ethernet frame in a broken-up format that is more accessible by components. For information on the class definition, see the EthernetFrame.h header file located in ...\ARM\FastModelPortfolio_X.Y\include\components\VirtualEthernet\Protocol\*

Parameters

Table 5.127 provides a description of the configuration parameters for the SMSC_91C111 component.

Table 5.127. SMSC_91C111 configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
enabledUsed for sending Ethernet frames between components.Booleantrue/falsefalse
mac_addressMAC address to use on hostStringsee mac_address parameter00:02:f7: ef:00:02
promiscuousPuts host Ethernet controller into promiscuous mode, for instance when sharing the Ethernet controller with the host OS.Booleantrue/falsetrue

mac_address parameter

There are two options for the mac_address parameter.

If a MAC address is not specified, when the simulator is run it takes the default MAC address, which is randomly-generated. This provides some degree of MAC address uniqueness when running models on multiple hosts on a local network.

Note

DHCP servers are used to allocate IP addresses, but because they sometimes do this based on the MAC address provided to them, then using random MAC addresses might interact unfortunately with some DHCP servers.

Registers

Table 5.128, Table 5.129, Table 5.130 and Table 5.131 provide descriptions of the configuration registers for the SMSC_91C111 component.

The SMSC_91C111 91C111 uses a banked register model of primarily 16 bit registers. There are also indirectly accessible registers for the PHY unit.

Bank 0 register

Table 5.128 lists the SMSC_91C111 bank 0 registers.

Table 5.128. SMSC_91C111 bank 0 registers

Register nameOffsetAccessDescription
TCR0x0read/writeTransmit control
EPH0x2read onlyStatus of last transmitted frame
RCR0x4read/writeReceive control
COUNTER0x6read/writeMAC statistics
MIR0x8read/writeMemory information
RPCR0xAread/writeReceive/PHY control
BANK0xEread/writeBank select

Bank 1 register

Table 5.129 lists the SMSC_91C111 bank 1 registers.

Table 5.129. SMSC_91C111 bank 1 registers

Register nameOffsetAccessDescription
CONFIG0x0read/writeConfiguration
BASE0x2read/writeBase address
IA0_10x4read/writeMAC address 0, 1
IA2_30x6read/writeMAC address 2, 3
IA4_50x8read/writeMAC address 4, 5
GP0xAread/writeGeneral purpose
CONTROL0xCread/writeControl
BANK0xEread/writeBank select

Bank 2 register

Table 5.130 lists the SMSC_91C111 bank 2 registers.

Table 5.130. SMSC_91C111 bank 2 registers

Register nameOffsetAccessDescription
MMU_COMMAND0x0read/writeMMU commands
PNR0x2read/writePacket number
ALLOCATED0x3read/writeAllocated packet number
FIFO_PORTS0x4read/writeTx/Rx FIFO packet number
POINTER0x6read/writeAddress to access in Tx/Rx packet
DATA0x8read/writeData register[a]
INTERRUPT0xCread/writeInterrupt status
INTERRUPT_MASK0xDread/writeInterrupt mask
BANK0xEread/writeBank select

[a] The data register can be accessed as 8, 16 or 32 bits and adjusts the pointer accordingly.


Bank 3 register

Table 5.131 lists the SMSC_91C111 bank 3 registers.

Table 5.131. SMSC_91C111 bank 3 registers

Register nameOffsetAccessDescription
MT0_10x0read/writeMulticast table 0, 1
MT2_30x2read/writeMulticast table 2, 3
MT4_50x4read/writeMulticast table 4, 5
MT6_70x6read/writeMulticast table 6, 7
MGMT0x8read/writeManagement interface
REVISION0xAread onlyChip revision ID
ERCV0xCread/writeEarly receive
BANK0xEread/writeBank select

Debug features

The SMSC_91C111 component has no debug features.

Verification and testing

The SMSC_91C111 component has been tested as part of the VE example system using VE test suites and by booting operating systems.

Performance

The SMSC_91C111 component is not expected to significantly affect the performance of a PV system.

Library dependencies

The SMSC_91C111 component has no dependencies on external libraries.

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