5.4.2. PL011_Uart component

The PL011_Uart component provides a programmer’s view model of the PL011_UART PrimeCell component as described in its technical reference manual. See PrimeCell UART (PL011) r1p4 Technical Reference Manual.

Note

The PL011_Uart component does not implement the DMA functionality of the PL011 PrimeCell.

Figure 5.23 shows a view of the component in System Canvas.

Figure 5.23. PL011_Uart in System Canvas

PL011_Uart in System Canvas

This component is written in LISA+.

Ports

Table 5.28 provides a brief description of the PL011_Uart component ports. For more information, see the PL011 technical reference manual.

Table 5.28. PL011_Uart ports

NamePort protocolTypeDescription
pvbusPVBusSlaveSlave port for connection to PV bus master/decoder.
intrSignalMasterInterrupt signaling.
clk_in_refClockSignalSlaveClock input, typically 14.745MHz, which sets the master transmit/receive rate.
serial_outSerialDataMasterUsed to communicate with a serial device, such as a terminal.

SerialData protocol for PL011_Uart

The PL011_Uart component has one additional protocol, SerialData. The serial data protocol is implemented as a parallel interface for efficiency. All communication is driven by the master port.

dataTransmit(uint16_t data) : void

Used by the master to send data to the slave. See Table 5.29 for bit definitions.

Table 5.29. Bits for dataTransmit()

BitsFunction
15:8reserved
7:0transmit data

dataReceive(void) : uint16_t

Used by the master to receive data from the slave. See Table 5.30 for bit definitions.

Table 5.30. Bits for dataReceive()

BitsFunction
15:13reserved
12set when no data available for reading
11reserved
10break error
9:8reserved
7:0receive data

signalsSet(uint8_t signal) : void

Used by the master to get the current signal status. See Table 5.31 for bit definitions.

Table 5.31. Bits for signalsSet()

BitsFunction
7Out1
6Out2
5RTS
4DTR
3:0reserved

signalsGet() : uint8_t

Used by the master to get the current signal status. See Table 5.32 for bit definitions.

Table 5.32. Bits for signalsGet()

BitsFunction
7:4Reserved
3DCD
2DSR
1CTS
0RI

Parameters

Table 5.33 lists the parameters used by the PL011_Uart component.

Table 5.33. PL011_Uart configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
baud_rateBaud rateInteger-38400
clock_rateClock rate for PL011Integer-14745600
in_fileInput fileString-[empty string]
in_file_escape_sequenceInput file escape sequenceString-##
out_fileOutput fileString-[empty string]
shutdown_on_eotShutdown simulation when an EOT (ASCII 4) character is transmitted.Booleantrue/falsefalse
uart_enableEnables UART when the system startsBooleantrue/falsefalse
unbuffered_output Unbuffered outputBooleantrue/falsefalse
untimed_fifos[a]Controls the rate at which serial data is transferred between the Tx/Rx FIFOs of the UART and the SerialData port.Booleantrue/falsefalse

[a] When false, characters of serial data are clocked to/from the SerialData port at a rate controlled by the clk_in_ref clock rate and the baud-rate-divider configuration of the UART clock. Enabling untimed_fifos permits serial data to be sent/received as fast as it can be generated/consumed. The modem control signals are still generated correctly, so the UART is not able to transmit data faster than the receiving end can handle. (For example, TelnetTerminal uses the CTS signal to avoid overflowing its TCP/IP buffer).


Registers

Table 5.34 gives a description of the configuration registers for the PL011_Uart component.

Table 5.34. PL011_Uart registers

Register nameOffsetAccessDescription
UARTDR0x00read/writeData register.
UARTRSR0x04read onlyReceive status register.
UARTECR0x04write onlyError clear register.
UARTFR0x18read onlyFlag register.
UARTILPR0x20read/writeIrDA low-power counter[a].
UARTIBRD0x24read/writeInteger baud rate divisor.
UARTFBRD0x28read/writeFractional baud rate divisor.
UARTLCR_H0x2Cread/writeLine control register, high byte.
UARTCR0x30read/writeControl register.
UARTFLS0x34read/writeInterrupt FIFO level select.
UARTMSC0x38read/writeInterrupt mask set/clear.
UARTRIS0x3Cread onlyRaw interrupt status.
UARTMIS0x40read onlyMasked interrupt register.
UARTICR0x44write onlyInterrupt clear register.
UARTDMACR0x48read/writeDMA control register[a].

[a] Not implemented.


Debug features

The PL011_Uart component has no debug features.

Verification and testing

The PL011_Uart component has been tested as part of the VE example system using VE test suites and by booting operating systems.

Performance

The PL011_Uart component is not expected to significantly affect the performance of a PV system. However, at very high baud rates such as in excess of 1MHz, simulation performance might be reduced.

Library dependencies

The PL011_Uart component has no dependencies on external libraries.

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