5.4.38. ICS307 component

The ICS307 component implements a programmer’s view model of an ICS307 clock divider. It can be used to convert the rate of one ClockSignal to another ClockSignal by application of configurable multiplier, divider and scale values.

The Divider ratio can be set by startup parameters or at runtime by a configuration port. Changes to the input ClockSignal rate and divider ratio are reflected immediately by the output ClockSignal ports.

The divisor ratio is determined by three values:

To calculate the divisor ratio, use:

Divisor = ((rdw+2) * scale) / (2 * (vdw+8)) 

where scale is derived from a table indexed by od, shown in Table 5.110:

Table 5.110. od to scale conversion


The default values of vdw, rdw and od are 4, 6 and 3 to give a default divisor rate of:

((6+2) * 4) / (2 * (4+8)) = 4/3

Figure 5.60 shows a view of the component in System Canvas.

Figure 5.60. ICS307 in System Canvas

ICS307 in System Canvas

This component is written in LISA+.


Table 5.111 provides a brief description of the ports.

Table 5.111. ICS307 ports

NamePort protocolTypeDescription
clk_inClockSignalSlaveMaster clock rate
clk_out_clk1ClockSignalMasterModified clock rate
clk_out_refClockSignalMasterPass through of master clock rate for divider chaining
configurationICS307ConfigurationSlaveConfiguration port for setting divider ratio dynamically


The ICS307 has one additional protocol.

The ICS307Configuration protocol permits you to set the divider ratio of an ICS307 component at runtime. The output clock rate is altered accordingly and any dependent components should react to the clock rate change according to their defined behavior.

setConfiguration(uint32_t vdw, uint32_t rdw,uint32_t od): void

Sets the parameters used to derive the clock divider ratio.


must be in the range 0-255


must be in the range 0-255


must be in the range 0-7.


Table 5.112 provides a description of the configuration parameters for the ICS307 component.

Table 5.112. ICS307 configuration parameters

Parameter nameDescriptionTypeAllowed valueDefault value
vdwUsed to calculate clock divider ratioInteger0-2554
rdrUsed to calculate clock divider ratioInteger0-2556
odUsed to calculate clock divider ratioInteger0-73


The ICS307 component has no registers.

Debug features

The ICS307 component has no debug features.

Verification and testing

The ICS307 component has been tested as part of the VE example system using VE test suites and by booting operating systems.


The ICS307 component is not expected to significantly affect the performance of a PV system. However, modifying the ICS307 timing parameters is relatively slow, so you are discouraged from doing so too often.

Library dependencies

The ICS307 component has no dependencies on external libraries.

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