5.4.20. PL192_VIC component

The PL192 is a Vectored Interrupt Controller (VIC) used to aggregate interrupts and generate interrupt signals to the ARM processor. When coupled to an ARM processor that provides a VIC port, routing to the appropriate interrupt handler can be optionally performed in hardware, reducing interrupt latency. The PL192_VIC can also be daisy-chained with other PL192 VICs to permit more than 32 interrupts. The VIC supports hardware and software prioritization of interrupts. For more information, see the VIC documentation. See ARM PrimeCell Vectored Interrupt Controller (PL192) Technical Reference Manual.

Figure 5.41 shows a view of the component in System Canvas.

Figure 5.41. PL192_VIC in System Canvas

PL192_VIC in System Canvas

This component is written in LISA+.

Ports

Table 5.69 provides a brief description of the PL192_VIC component ports. For more information, see the component documentation.

Table 5.69. PL192_VIC ports

NamePort protocolTypeDescription
VICIntSource [32]SignalSlaveInterrupt source input sources
VICVECTADDRINValueSlaveUsed to receive vector address when daisy chained
nVICFIQINSignalSlaveUsed to receive FIQ signal when daisy chained
nVICIRQINSignalSlaveUsed to receive IRQ signal when daisy chained
pvbusPVBusSlaveSlave port for connection to PV bus master/decoder
VICIRQACKSignalSlaveReceive acknowledge signal from next level VIC or processor
VICIRQACKOUTSignalMasterUsed to send out acknowledge signals when daisy chained
VICVECTADDROUTValueMasterUsed to send vector address to next level VIC or processor
nVICFIQSignalMasterSend out FIQ signal to the next level VIC or CPI
nVICIRQSignalMasterSend out IRQ signal to the next level VIC or processor

Additional protocols

The PL192_VIC component has no additional protocols.

Parameters

The PL192_VIC component has no parameters.

Registers

Table 5.70 provides a description of the configuration registers for the PL192_VIC component.

Table 5.70. PL192_VIC registers

Register nameOffsetAccessDescription
IRQSTATUS0x000read onlyIRQ status register
FIQSTATUS0x004read onlyFIQ status register
RAWINTR0x008read onlyRaw interrupt status register
INTSELECT0x00Cread/writeInterrupt select register
INTENABLE0x010read/writeInterrupt enable register
INTENCLEAR0x014write onlyInterrupt enable clear register
SOFTINT0x018read/writeSoftware interrupt register
SOFTINTCLEAR0x01Cwrite onlySoftware interrupt clear register
PROTECTION0x020read/writeProtection enable register
SWPRIORITY0x024read/writeSoftware priority mask
PRIORITYDAISY0x028read/writeVector priority register for daisy chain
VECTADDR[0:31]0x100 - 0x17Cread/write32 vector addresses
VECTPRIORITY[0:31]0x200 - 0x27Cread/write32 priority registers
VICADDRESS0xF00read/writeVector address register

Debug features

The PL192_VIC component has no debug features.

Verification and testing

The PL192_VIC has been run against the RTL validation suite and has been successfully used in validation platforms.

Performance

The PL192_VIC component is not expected to significantly affect the performance of a PV system.

Library dependencies

The PL192_VIC component has no dependencies on external libraries.

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