The PL192 is a Vectored Interrupt Controller (VIC) used to aggregate interrupts and generate interrupt signals to the ARM processor. When coupled to an ARM processor that provides a VIC port, routing to the appropriate interrupt handler can be optionally performed in hardware, reducing interrupt latency. The PL192_VIC can also be daisy-chained with other PL192 VICs to permit more than 32 interrupts. The VIC supports hardware and software prioritization of interrupts. For more information, see the VIC documentation. See ARM PrimeCell Vectored Interrupt Controller (PL192) Technical Reference Manual.
Figure 5.41 shows a view of the component in System Canvas.
This component is written in LISA+.
Table 5.69 provides a brief description of the PL192_VIC component ports. For more information, see the component documentation.
Table 5.69. PL192_VIC ports
| Name | Port protocol | Type | Description |
|---|---|---|---|
| VICIntSource [32] | Signal | Slave | Interrupt source input sources |
| VICVECTADDRIN | Value | Slave | Used to receive vector address when daisy chained |
| nVICFIQIN | Signal | Slave | Used to receive FIQ signal when daisy chained |
| nVICIRQIN | Signal | Slave | Used to receive IRQ signal when daisy chained |
| pvbus | PVBus | Slave | Slave port for connection to PV bus master/decoder |
| VICIRQACK | Signal | Slave | Receive acknowledge signal from next level VIC or processor |
| VICIRQACKOUT | Signal | Master | Used to send out acknowledge signals when daisy chained |
| VICVECTADDROUT | Value | Master | Used to send vector address to next level VIC or processor |
| nVICFIQ | Signal | Master | Send out FIQ signal to the next level VIC or CPI |
| nVICIRQ | Signal | Master | Send out IRQ signal to the next level VIC or processor |
Table 5.70 provides a description of the configuration registers for the PL192_VIC component.
Table 5.70. PL192_VIC registers
| Register name | Offset | Access | Description |
|---|---|---|---|
| IRQSTATUS | 0x000 | read only | IRQ status register |
| FIQSTATUS | 0x004 | read only | FIQ status register |
| RAWINTR | 0x008 | read only | Raw interrupt status register |
| INTSELECT | 0x00C | read/write | Interrupt select register |
| INTENABLE | 0x010 | read/write | Interrupt enable register |
| INTENCLEAR | 0x014 | write only | Interrupt enable clear register |
| SOFTINT | 0x018 | read/write | Software interrupt register |
| SOFTINTCLEAR | 0x01C | write only | Software interrupt clear register |
| PROTECTION | 0x020 | read/write | Protection enable register |
| SWPRIORITY | 0x024 | read/write | Software priority mask |
| PRIORITYDAISY | 0x028 | read/write | Vector priority register for daisy chain |
| VECTADDR[0:31] | 0x100 - 0x17C | read/write | 32 vector addresses |
| VECTPRIORITY[0:31] | 0x200 - 0x27C | read/write | 32 priority registers |
| VICADDRESS | 0xF00 | read/write | Vector address register |
The PL192_VIC has been run against the RTL validation suite and has been successfully used in validation platforms.
The PL192_VIC component is not expected to significantly affect the performance of a PV system.
PDF version